Stacked semiconductor device and fabrication method for same
View Patent ↗A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.
1. A semiconductor device comprising:
a semiconductor chip including a plurality of electrodes thereon;
a plurality of terminal formation pads provided over the semiconductor chip;
a wiring layer provided between the semiconductor chip and the terminal formation pads, the wiring layer including a plurality of wirings that are electrically connecting the electrodes of the semiconductor chip to the terminal formation pads;
a first insulating layer provided over the wiring layer to encapsulate the semiconductor chip;
a linking connection pad formed on the first insulating layer, the linking connection pad including an upper surface that is kept uncovered by the first insulating layer and a lower surface that is in contact with the first insulating layer;
a linking wiring extending from one of the wirings of the wiring layer, penetrating the first insulating layer and reaching the linking connection pad; and
a plurality of solder balls mounted on the terminal formation pads, respectively.
2. The semiconductor device according to claim 1 , wherein the linking connection pad is arranged at a position overlapping to one of the terminal pads in plane view.
3. The semiconductor device according to claim 1 , wherein the one of the wirings is electrically connected to both of a corresponding one of the terminal pads and the linking connection pad.
4. The semiconductor device according to claim 1 , wherein the first insulating layer comprises an encapsulant covering the semiconductor chip and a protective layer covering the linking wiring.
5. The semiconductor device according to claim 4 , wherein the linking wiring is disposed between the encapsulant and the protective layer.
6. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a first surface on which the plurality of electrodes formed, and the first surface faces the wiring layer.
7. The semiconductor device according to claim 1 , wherein the semiconductor chip includes a first surface on which the plurality of electrodes formed and a second surface opposite to the first surface, and the second surface faces the wiring layer.
8. The semiconductor device according to claim 1 , further comprising:
a second insulating layer provided on the wiring layer, the wiring layer being disposed between the semiconductor chip and the second insulating layer.
9. The semiconductor device according to claim 1 , wherein the linking connection pad includes a side surface joining the upper surface and the lower surface, the side surface is in contact with the first insulating layer.
10. The semiconductor device according to claim 1 , further comprising:
an upper package including an upper semiconductor chip and an upper electrode electrically connecting to the upper semiconductor chip, the upper package being stacked over the first insulating layer so that the upper electrode electrically connects to the linking connection pad.
11. The semiconductor device according to claim 6 , wherein each of the electrodes of the semiconductor chip is a bump electrode.
12. A semiconductor device comprising:
a plurality of wirings;
a plurality of terminal formation pads each electrically connected to an associated one of the wirings;
a plurality of external electrodes formed on the terminal formation pads, respectively;
a semiconductor chip including a plurality of electrodes, each of the electrodes being electrically connected to a corresponding one of the wirings;
a cover layer covering the semiconductor chip such that the semiconductor chip is between the cover layer and the external electrodes;
at least one linking connection pad formed on the cover layer such that an upper surface of the linking connection pad is kept uncovered by the cover layer and a lower surface of the linking connection pad is in contact with the cover layer; and
at least one linking wiring extending from one of the wirings, penetrating the cover layer and reaching the linking connection pad.
13. The semiconductor device according to claim 12 , wherein the linking connection pad is arranged at a position overlapping to one of the terminal formation pads in plane view.
14. The semiconductor device according to claim 12 , wherein the one of the wirings is electrically connected to both of a corresponding one of the terminal formation pads and the linking connection pad.
15. The semiconductor device according to claim 12 , further comprising:
an insulating layer provided between the wirings and the terminal formation pads.
16. The semiconductor device according to claim 12 , wherein the semiconductor 3 chip includes a first surface on which the plurality of electrodes formed, and the first surface faces the wirings.
17. The semiconductor device according to claim 12 , wherein the semiconductor chip includes a first surface on which the plurality of electrodes formed and a second surface opposite to the first surface, and the second surface faces the wirings.
18. The semiconductor device according to claim 12 , wherein the linking connection pad includes a side surface joining the upper surface and the lower surface, the side surface of the linking connection pad is in contact with the cover layer.
19. The semiconductor device according to claim 12 , further comprising:
an upper package including an upper semiconductor chip and an upper electrode electrically connecting to the upper semiconductor chip, the upper package being stacked over the cover layer so that the upper electrode electrically connects to the linking connection pad.
20. The semiconductor device according to claim 17 , wherein each of the electrodes of the semiconductor chip is a bump electrode.