IP Library Granted Patent US 9,041,370
Granted Patent B2
US 9,041,370 · App. 13/544,815 · Granted May 26, 2015

Charge pump regulator circuit with a variable drive voltage ring oscillator

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Quick Facts
Patent No.
US 9,041,370
App. No.
13/544,815
Granted
May 26, 2015
Kind
B2
Abstract

A charge pump regulator circuit includes a voltage controlled oscillator and a plurality of charge pumps. The voltage controlled oscillator has a plurality of inverter stages connected in series in a ring. A plurality of oscillating signals is generated from outputs of the inverter stages. Each oscillating signal has a frequency or amplitude or both that are variable dependent on a variable drive voltage. Each oscillating signal is phase shifted from a preceding oscillating signal. Each charge pump is connected to a corresponding one of the inverter stages to receive the oscillating signal produced by that inverter stage. Each charge pump outputs a voltage and current. The output of each charge pump is phase shifted from the outputs of other charge pumps. A combination of the currents thus produced is provided at about a voltage level to the load.

Claims (59)

1. A charge pump regulator circuit that powers a variable load, the charge pump regulator circuit comprising:

a voltage controlled oscillator comprising a plurality of inverter stages connected in series in a ring, each of the plurality of inverter stages producing an oscillating signal that is provided to a next one of the plurality of inverter stages, each oscillating signal having a frequency and amplitude that are both variable dependent on a variable drive voltage that serves as a supply voltage for the plurality of inverter stages; and

a plurality of charge pumps, each one of the plurality of charge pumps being connected to a corresponding one of the plurality of inverter stages to receive the oscillating signal produced by that inverter stage, the plurality of charge pumps outputting a current at about a voltage level to the variable load.

2. The charge pump regulator circuit of claim 1 , wherein:

each charge pump comprises a plurality of charge pump stages arranged in series; and

each oscillating signal forms a positive oscillating signal and a negative oscillating signal that are applied in an alternating manner to consecutive charge pump stages in the plurality of charge pump stages.

3. The charge pump regulator circuit of claim 1 , wherein:

the voltage and current output by the plurality of charge pumps is dependent on the frequency and amplitude of the oscillating signals.

4. The charge pump regulator circuit of claim 1 , wherein:

when the variable drive voltage provided to the plurality of inverter stages is reduced, the frequency and amplitude of each oscillating signal is reduced; and

when the variable drive voltage provided to the plurality of inverter stages is increased, the frequency and amplitude of each oscillating signal is are increased.

5. The charge pump regulator circuit of claim 4 , wherein:

when the frequency and amplitude of each oscillating signal is reduced, a noise level in the current and voltage provided to the variable load by the plurality of charge pumps is reduced; and

when the frequency and amplitude of each oscillating signal is increased, the noise level in the current and voltage provided to the variable load by the plurality of charge pumps is increased.

6. The charge pump regulator circuit of claim 1 , further comprising:

a feedback loop that generates the variable drive voltage for the plurality of inverter stages depending on feedback of the voltage level provided to the variable load.

7. The charge pump regulator circuit of claim 1 , wherein:

each oscillating signal is phase shifted from a previous oscillating signal in the ring.

8. The charge pump regulator circuit of claim 7 , wherein:

an output of each charge pump is phase shifted from the output of other charge pumps.

9. The charge pump regulator circuit of claim 1 , wherein:

the plurality of charge pumps are arranged in parallel.

10. A charge pump regulator circuit that powers a variable load, the circuit comprising:

a voltage controlled oscillator comprising a plurality of inverter stages connected in series in a ring, each of the plurality of inverter stages producing a phase shifted oscillating signal that is provided to a next inverter stage in the plurality of inverter stages, and each phase shifted oscillating signal having a frequency and amplitude that are both variable dependent on a variable drive voltage that serves as a supply voltage for the plurality of inverter stages; and

a plurality of charge pumps arranged in parallel, each charge pump being connected to a corresponding inverter stage in the plurality of inverter stages to receive the phase shifted oscillating signal produced by the corresponding inverter stage, each charge pump outputting a voltage and a current, the output of each charge pump being phase shifted, the current from each charge pump being combined and provided at about a voltage level to the variable load.

11. The charge pump regulator circuit of claim 10 , wherein:

each charge pump comprises a plurality of charge pump stages arranged in series; and

each oscillating signal forms a positive oscillating signal and a negative oscillating signal that are applied in an alternating manner to consecutive charge pump stages in the plurality of charge pump stages.

12. The charge pump regulator circuit of claim 10 , further comprising:

a feedback loop that provides a drive voltage that powers the plurality of inverter stages, a change in the drive voltage causing the plurality of inverter stages to change a frequency or an amplitude of each phase shifted oscillating signal, which causes a change in a level of the voltage and current provided to the variable load by the plurality of charge pumps while attempting to maintain the voltage level thereof.

13. The charge pump regulator circuit of claim 12 , wherein:

when the frequency and amplitude of the oscillating signals are reduced, a noise level in the current and voltage provided to the variable load by the plurality of charge pumps is reduced; and

when the frequency and amplitude of the oscillating signals are increased, the noise level in the current and voltage provided to the variable load by the plurality of charge pumps is increased.

14. The charge pump regulator circuit of claim 12 , wherein:

when the drive voltage provided to the plurality of inverter stages is reduced, the frequency and amplitude of each phase shifted oscillating signal is reduced; and

when the drive voltage provided to the plurality of inverter stages is increased, the frequency and amplitude of each phase shifted oscillating signal is increased.

15. A method comprising:

generating a plurality of oscillating signals from a voltage controlled oscillator having a plurality of inverter stages connected in series in a ring;

varying a frequency and an amplitude of the plurality of oscillating signals depending on a variable drive voltage that serves as a supply voltage for the plurality of inverter stages;

providing the plurality of oscillating signals as inputs to a plurality of charge pumps;

generating a plurality of charge pump output voltages and currents; and

providing a combination of the plurality of charge pump output currents at a voltage level to a load.

16. The method of claim 15 , wherein:

each oscillating signal is phase shifted from a previous one of the plurality of oscillating signals in the ring;

the plurality of charge pumps are arranged in parallel;

each charge pump corresponds to one of the plurality of inverter stages; and

an output of each charge pump is phase shifted from the output of each other charge pump.

17. The method of claim 15 , further comprising:

varying both the frequency and the amplitude of the plurality of oscillating signals depending on the variable drive voltage applied to the plurality of inverter stages.

18. The method of claim 17 , further comprising:

regulating the plurality of oscillating signals to regulate the plurality of charge pump output currents provided at about the voltage level in order to respond to variations in the load.

19. The method of claim 18 , further comprising:

regulating the plurality of oscillating signals with a feedback loop that produces the variable drive voltage for powering the plurality of inverter stages.

20. The method of claim 19 , further comprising:

regulating the plurality of oscillating signals to reduce the frequency and amplitude thereof when the variable drive voltage is reduced; and

regulating the plurality of oscillating signals to increase the frequency and amplitude thereof when the variable drive voltage is increased.

21. The method of claim 20 , further comprising:

decreasing the plurality of charge pump output voltages and currents when the frequency and amplitude of the plurality of oscillating signals are reduced; and

increasing the plurality of charge pump output voltages and currents when the frequency and amplitude of the plurality of oscillating signals are increased.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: QUALCOMM SWITCH CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 038794/0663 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS PATENT NUMBER 9029901 TO THE CORRECT PATENT NO. 9029201 AS PREVIOUSLY RECORDED ON REEL 036812 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST AGAINST ALL PATENTS SET FORTH HEREIN. Recorded Oct 20, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036907/0785 →
CHANGE OF NAME Recorded Oct 16, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: QUALCOMM SWITCH CORP.
Reel/Frame 036877/0140 →
TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST (PATENTS) Recorded Oct 7, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036812/0429 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 028752 FRAME: 0792. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 21, 2015
From: MOLIN, STUART B; LOU, PERRY; KEMERLING, CLINT
To: IO SEMICONDUCTOR INCORPORATED
Reel/Frame 036148/0498 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033134 FRAME: 0338. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 15, 2015
From: IO SEMICONDUCTOR INCORPORATED
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 036109/0237 →
CHANGE OF NAME Recorded Jun 11, 2014
From: IO SEMICONDUCTOR, INC.
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 033134/0338 →
SECURITY AGREEMENT Recorded Feb 4, 2013
From: IO SEMICONDUCTOR INCORPORATED
To: HSBC BANK AUSTRALIA LIMITED
Reel/Frame 029751/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2012
From: MOLIN, STUART B.; LOU, PERRY; KEMERLING, CLINT
To: IO SEMICONDUCTOR, INC.
Reel/Frame 028752/0792 →