IP Library Granted Patent US 9,356,158
Granted Patent B2
US 9,356,158 · App. 13/554,867 · Granted May 31, 2016

Electronic device including a tunnel structure

Inventors: Thierry Coffi Herve Yao (Portland, OR); Gregory James Scott (Inkom, ID)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L29/7883G11C16/0433G11C16/14H01L27/11558
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Quick Facts
Patent No.
US 9,356,158
App. No.
13/554,867
Granted
May 31, 2016
Kind
B2
Abstract

An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Claims (60)

1. A process of forming an electronic device comprising:

providing a substrate including a lightly doped region at a primary surface, wherein the lightly doped region has a first conductivity type;

forming a tunnel dielectric layer over the substrate;

forming a second electrode of the tunnel structure over the tunnel dielectric layer, wherein at least a part of the second electrode has the first conductivity type;

forming a first intermediate doped region within a portion of the lightly doped region, wherein the first intermediate doped region is at the primary surface, abuts the lightly doped region, has a second conductivity type opposite the first conductivity type, and has a dopant concentration that is greater than a dopant concentration of the lightly doped region;

forming a first heavily doped region at the primary surface, wherein the first heavily doped region abuts the first intermediate doped region and has the second conductivity type and a concentration that is higher than the first intermediate doped region;

forming a second heavily doped region at the primary surface, wherein the second heavily doped region is at the primary surface, contacts the lightly doped region, has the first conductivity type and a concentration that is higher than the first intermediate doped region, wherein from a top view, the first heavily doped region is disposed between the first intermediate doped region and the second heavily doped region; and

forming a second intermediate doped region spaced apart from the first intermediate doped region, wherein:

the second electrode has a first side and a second side;

the first intermediate doped region is disposed closer to the first side than the second side;

the second intermediate doped region is disposed closer to the second side than the first side; and

the second electrode overlies a portion of the first intermediate doped region and a portion of the second intermediate doped region.

2. The process of claim 1 , further comprising forming a strapping member that electrically connects the first and second heavily doped regions together.

3. The process of claim 2 , wherein the strapping member comprises a transition metal silicide.

4. The process of claim 2 , wherein the strapping member does not overlie the first intermediate doped region.

5. The process of claim 1 , further comprising forming a sidewall spacer adjacent to the second electrode, wherein the sidewall spacer overlies the first intermediate doped region but does not overlie the first or second heavily doped region.

6. The process of claim 5 , further comprising forming a mask after forming the second electrode and the first intermediate doped region, wherein: the mask defines an opening over the second electrode and only a part of the first intermediate region; and forming the first heavily doped region comprising implanting a dopant through the opening in the mask and into the lightly doped region.

7. The process of claim 6 , wherein the mask includes a mask feature that covers the second electrode and the sidewall spacer.

8. The process of claim 1 , wherein forming the first intermediate region comprises doping a portion of the lightly doped region to a dopant concentration no greater than approximately 1×10 18 atoms/cm 3 .

9. The process of claim 1 , wherein forming the second electrode is performed such that substantially all of the second electrode has the first conductivity type.

10. The process of claim 1 , wherein forming the second heavily doped region is performed such that the entire second heavily doped region is disposed above a bottom surface of the first heavily doped region.

11. The process of claim 1 , further comprising:

forming a field isolation region within the substrate,

wherein the second heavily doped region is disposed between the field isolation region and the first heavily doped region.

12. The process of claim 1 , wherein the first heavily doped region has a junction depth deeper than the first intermediate doped region.

13. A process of forming an electronic device comprising:

providing a substrate including a lightly doped region at a primary surface, wherein the lightly doped region has a first conductivity type;

forming a tunnel dielectric layer over the substrate;

forming a second electrode of the tunnel structure over the tunnel dielectric layer, wherein at least a part of the second electrode has the first conductivity type;

forming a first intermediate doped region within a portion of the lightly doped region, wherein the first intermediate doped region is at the primary surface, abuts the lightly doped region, has a second conductivity type opposite the first conductivity type, and has a dopant concentration that is greater than a dopant concentration of the lightly doped region;

forming a first heavily doped region at the primary surface, wherein the first heavily doped region abuts the first intermediate doped region and has the second conductivity type and a concentration that is higher than the first intermediate doped region;

forming a second heavily doped region at the primary surface, wherein the second heavily doped region is at the primary surface, contacts the lightly doped region, has the first conductivity type and a concentration that is higher than the first intermediate doped region; and

forming a mask after forming the second electrode and the first intermediate doped region, wherein:

the mask defines an opening over the second electrode and only a part of the first intermediate region; and

forming the first heavily doped region comprising implanting a dopant through the opening in the mask and into the lightly doped region,

wherein from a top view, the first heavily doped region is disposed between the first intermediate doped region and the second heavily doped region.

14. The process of claim 13 , further comprising forming a strapping member that electrically connects the first and second heavily doped regions together.

15. The process of claim 13 , wherein the mask includes a mask feature that covers the second electrode and the sidewall spacer.

16. The process of claim 13 , further comprising forming a sidewall spacer adjacent to the second electrode, wherein the sidewall spacer overlies the first intermediate doped region but does not overlie the first or second heavily doped region.

17. The process of claim 13 , wherein the second heavily doped region is formed after forming the first heavily doped region.

18. The process of claim 13 , further comprising forming a second intermediate doped region spaced apart from the first intermediate doped region, wherein:

the second electrode has a first side and a second side;

the first intermediate doped region is disposed closer to the first side than the second side;

the second intermediate doped region is disposed closer to the second side than the first side; and

the second electrode overlies a portion of the first intermediate doped region and a portion of the second intermediate doped region.

19. A process of forming an electronic device comprising:

providing a substrate including a lightly doped region at a primary surface, wherein the lightly doped region has a first conductivity type;

forming a tunnel dielectric layer over the substrate;

forming a second electrode of the tunnel structure over the tunnel dielectric layer, wherein at least a part of the second electrode has the first conductivity type, and wherein the second electrode is part of a floating gate electrode;

forming a first intermediate doped region within a portion of the lightly doped region, wherein the first intermediate doped region is at the primary surface, abuts the lightly doped region, has a second conductivity type opposite the first conductivity type, and has a dopant concentration that is greater than a dopant concentration of the lightly doped region;

forming a first heavily doped region at the primary surface, wherein the first heavily doped region abuts the first intermediate doped region and has the second conductivity type and a concentration that is higher than the first intermediate doped region;

forming a second heavily doped region at the primary surface, wherein the second heavily doped region is at the primary surface, contacts the lightly doped region, has the first conductivity type and a concentration that is higher than the first intermediate doped region,

wherein from a top view:

the first heavily doped region is disposed between the first intermediate doped region and the second heavily doped region, and

no electrode is disposed over the first and second heavily doped regions.

20. The process of claim 19 , further comprising forming a second intermediate doped region spaced apart from the first intermediate doped region, wherein:

the second electrode has a first side and a second side;

the first intermediate doped region is disposed closer to the first side than the second side;

the second intermediate doped region is disposed closer to the second side than the first side; and

the second electrode overlies a portion of the first intermediate doped region and a portion of the second intermediate doped region.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2012
From: YAO, THIERRY COFFI HERVE; SCOTT, GREGORY JAMES
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 028602/0925 →
Continuity (1)
Related Publication 20140021526A1 · Jan 23, 2014