Process of forming an electronic device including a nonvolatile memory cell
An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.
1. A process of forming an electronic device including a nonvolatile memory cell comprising:
forming a field isolation region within a substrate to define first, second, and third active regions, wherein the first, second, and third active regions are spaced apart from one another;
forming a floating gate electrode over the substrate and a part of the field isolation region, wherein the floating gate includes:
a first portion disposed over the first active region;
a second portion disposed over the second active region; and
a third portion disposed over the third active region;
forming an access gate electrode over the third active region, wherein the access gate electrode and the floating gate electrode are spaced apart from each other;
forming an intermediate doped region within the second active region and adjacent to the floating gate electrode, wherein the intermediate doped region has a first conductivity type;
forming a first heavily doped region within the second active region, wherein the first heavily doped region has the first conductivity type and a dopant concentration that is higher than the dopant concentration of the first intermediate doped region; and
forming a second heavily doped region within the second active region, wherein the second heavily doped region has a second conductivity type opposite the first conductivity type, and a dopant concentration that is higher than the dopant concentration of the first intermediate doped region,
wherein forming the intermediate doped region and the first and second heavily doped regions are performed such that, from a top view, the first heavily doped region is disposed between the intermediate doped region and the second heavily doped region.
2. The process of claim 1 , further comprising:
forming a first n-well region that includes the first active region;
forming a second n-well region that includes the second active region; and
forming a first p-well region within the third active region,
wherein the first conductivity type is p-type, and the second conductivity type is n-type.
3. The process of claim 1 , wherein forming the floating gate electrode is performed such that:
the first portion of the floating gate electrode has the second conductivity type, and the first active region has the first conductivity type;
at least part of the second portion of the floating gate electrode has the first conductivity type, and the second active region has the first conductivity type; and
the third portion of the floating gate electrode has the second conductivity type, and the third active region has the first conductivity type.
4. The process of claim 1 , further comprising:
forming a mask over the first, second, and third active regions, wherein the mask defines an opening disposed over a particular portion of the field isolation region; and
implanting a p-type dopant into the substrate at a location below the particular portion of the field isolation region.
5. The process of claim 1 , further comprising:
forming a metal-containing layer over field isolation region, the first, second, and third active regions, the floating gate electrode, and the access gate electrode;
reacting portions of the metal-containing layer and portions of the first, second, and third active regions, the floating gate electrode, and the access gate electrode to form metal-semiconductor members, wherein:
a first metal-semiconductor member is substantially coterminous with the floating gate electrode;
a second metal-semiconductor member is substantially coterminous with the access gate electrode; and
a third metal-semiconductor member electrically connects the first and second heavily doped regions and is spaced apart from the first metal semiconductor member; and
removing an unreacted portion of the metal-containing layer.
6. The process of claim 1 , wherein the floating gate electrode is a single conductive member.
7. The process of claim 1 , wherein the access gate electrode is part of a word line.
8. The process of claim 1 , wherein:
the first portion of the floating gate electrode has a p-type conductivity; and
the second and third portions of the floating gate electrode have an n-type conductivity.
9. The process of claim 8 , further comprising:
forming n-well regions that include the first and second active regions;
forming a p-well region that includes the third active region.
10. The process of claim 9 , wherein:
forming the field isolation region comprises forming the field isolation region within the substrate to define a fourth active region; and
forming the p-well region comprises forming the p-well region that further includes the fourth active region.
11. The process of claim 10 , further comprising forming a well contact region within the fourth active region.
12. The process of claim 11 , wherein no gate electrode overlies the fourth active region.
13. A process of forming an electronic device including a nonvolatile memory cell comprising:
forming a field isolation region within a substrate to define first, second, and third active regions, wherein the first, second, and third active regions are spaced apart from one another;
forming a floating gate electrode over the substrate and a part of the field isolation region, wherein the floating gate includes:
a first portion disposed over the first active region;
a second portion disposed over the second active region; and
a third portion disposed over the third active region;
forming an access gate electrode over the third active region, wherein the access gate electrode and the floating gate electrode are spaced apart from each other;
forming an intermediate doped region within the second active region and adjacent to the floating gate electrode, wherein the intermediate doped region has a first conductivity type;
forming a first heavily doped region within the second active region, wherein the first heavily doped region has the first conductivity type and a dopant concentration that is higher than the dopant concentration of the first intermediate doped region; and
forming a second heavily doped region within the second active region, wherein the second heavily doped region has a second conductivity type opposite the first conductivity type, and a dopant concentration that is higher than the dopant concentration of the first intermediate doped region,
wherein forming the intermediate doped region and the first and second heavily doped regions are performed such that, from a top view, the first heavily doped region is disposed between the intermediate doped region and the second heavily doped region, and wherein:
the first portion of the floating gate electrode includes an electrode of a capacitor;
the second portion of the floating gate electrode includes an electrode of a tunnel structure;
the third portion of the floating gate electrode includes a gate electrode of a state transistor; and
the capacitor, the tunnel structure, and the state transistor are spaced apart from one another.
14. The process of claim 13 , wherein the state transistor and the access transistor include portions that are within a same well region.
15. The process of claim 13 , further comprising:
forming a first n-well region that includes the first active region;
forming a second n-well region that includes the second active region; and
forming a first p-well region within the third active region,
wherein the first conductivity type is p-type, and the second conductivity type is n-type.
16. The process of claim 13 , wherein forming the floating gate electrode is performed such that:
the first portion of the floating gate electrode has the second conductivity type, and the first active region has the first conductivity type;
at least part of the second portion of the floating gate electrode has the first conductivity type, and the second active region has the first conductivity type; and
the third portion of the floating gate electrode has the second conductivity type, and the third active region has the first conductivity type.
17. The process of claim 13 , wherein the floating gate electrode is a single conductive member.
18. The process of claim 13 , further comprising:
forming a mask over the first, second, and third active regions, wherein the mask defines an opening disposed over a particular portion of the field isolation region; and
implanting a p-type dopant into the substrate at a location below the particular portion of the field isolation region.
19. The process of claim 13 , wherein the access gate electrode is part of a word line.
20. The process of claim 13 , further comprising:
forming a metal-containing layer over field isolation region, the first, second, and third active regions, the floating gate electrode, and the access gate electrode;
reacting portions of the metal-containing layer and portions of the first, second, and third active regions, the floating gate electrode, and the access gate electrode to form metal-semiconductor members, wherein:
a first metal-semiconductor member is substantially coterminous with the floating gate electrode;
a second metal-semiconductor member is substantially coterminous with the access gate electrode; and
a third metal-semiconductor member electrically connects the first and second heavily doped regions and is spaced apart from the first metal-semiconductor member; and
removing an unreacted portion of the metal-containing layer.