Multi-chip package for imaging systems
View Patent ↗A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate.
1. A multi-chip package, comprising:
a substrate;
a first integrated circuit mounted on the substrate;
a second integrated circuit stacked on top of the first integrated circuit;
a cover glass positioned over the second integrated circuit, wherein the cover glass is configured to receive incoming light that is captured using circuitry on the second integrated circuit; and
a ring-shaped adhesive layer formed between the first integrated circuit and the second integrated circuit, wherein the ring-shaped adhesive layer surrounds an empty hole interposed between the first and second integrated circuits.
2. The multi-chip package defined in claim 1 , wherein the first integrated circuit comprises an image signal processing integrated circuit, wherein the second integrated circuit comprises an image sensor integrated circuit, and wherein the circuitry on the second integrated circuit comprises a plurality of image sensor pixels.
3. The multi-chip package defined in claim 1 , wherein the adhesive layer comprises an adhesive material selected from the group consisting of: an epoxy-based adhesive, a rubber-based adhesive, a polyimide-based adhesive, a polyolefin-based adhesive, and an acrylic-based adhesive.
4. The multi-chip package defined in claim 1 , further comprising:
a support structure interposed between the cover glass and the second integrated circuit structure.
5. The multi-chip package defined in claim 1 , further comprising:
a support structure surrounding the first and second integrated circuit, wherein the support structure has a top surface supporting the cover glass and a bottom surface resting on the substrate.
6. The multi-chip package defined in claim 5 , further comprising:
an adhesive layer formed between the top surface of the supporting structure and the cover glass, wherein the cover glass, the supporting structure, and the substrate surrounds a space within which the first and second integrated circuits are contained, and wherein the space is devoid of air.
7. The multi-chip package defined in claim 1 , further comprising:
a sealing compound that hermetically seals the multi-chip package and that is formed from a different material than the ring-shaped adhesive layer.
8. A method for manufacturing a multi-chip package, comprising:
placing first and second integrated circuit dies on a substrate;
placing a cover glass over the first and second integrated circuit dies, wherein the cover glass is configured to receive incoming light that is captured using circuitry on the second integrated circuit die; and
forming a ring-shaped adhesive layer between the first and second integrated circuit dies, wherein the ring-shaped adhesive layer overlaps with wire bond pads formed on the first integrated circuit die, and wherein the ring-shaped adhesive layer surrounds an empty hole interposed between the first and second integrated circuits.
9. The method defined in claim 8 , wherein placing the first and second integrated circuit dies on the substrate comprises mounting the first integrated circuit die on the substrate and vertically stacking the second integrated circuit die on top of the first integrated circuit die.
10. The method defined in claim 9 , wherein the first integrated circuit die comprises an image signal processor die, wherein the second integrated circuit die comprises a image sensor die, and wherein the circuitry on the second integrated circuit die comprises a plurality of image sensor pixels formed on the image sensor die.
11. The method defined in claim 8 , further comprising:
forming a support structure on the substrate that suspends the cover glass over the second integrated circuit die.
12. The method defined in claim 11 , wherein the support structure has a lower surface that contacts the substrate and an upper surface that supports the cover glass.
13. The method defined in claim 12 , further comprising:
forming a layer of adhesive between the upper surface of the support structure and the cover glass to hermetically seal the multi-chip package.
14. The method defined in claim 13 , wherein the substrate, the cover glass, and the support structure form a cavity that surrounds the first and second integrated circuit dies.
15. The method defined in claim 14 , wherein the cavity is a vacuum.
16. The method defined in claim 8 , further comprising:
forming a ring-shaped support structure on the second integrated circuit die that suspends the cover glass over the second integrated circuit die.
17. The method defined in claim 8 , further comprising:
wire-bonding the first integrated circuit die to the substrate; and
wire-bonding the second integrated circuit die to the substrate, wherein signals are conveyed between the first and second integrated circuit dies via conductive traces formed in the substrate.
18. The method defined in claim 8 , further comprising:
after forming the ring-shaped adhesive layer between the first and second integrated circuit dies, disposing a sealant over the first and second integrated circuit dies to seal the multi-chip package.