Computer system including CPU or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits
A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.
1. A computer, comprising:
a connector that can be configured to couple to a console;
an integrated central processing unit and graphics subsystem in a single chip;
a Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and
a serial bit channel that couples to the connector, wherein the serial bit channel is adapted to transmit data packets in accordance with a Universal Serial Bus (USB) protocol;
wherein the integrated central processing unit and graphics subsystem outputs digital video display signals.
2. The computer of claim 1 , wherein the console further comprises a mass storage device configured to couple to the integrated central processing unit and graphics subsystem through the serial bit channel and the connector.
3. The computer system of claim 1 , wherein the console further comprises a user input device configured to couple to the integrated central processing unit and graphics subsystem through the serial bit channel and the connector.
4. The computer system of claim 1 , wherein the console comprises a Liquid Crystal Display (LCD) display configured to couple to the digital video display signals of the computer through the connector.
5. The computer system of claim 1 , wherein the computer couples to the console through the LVDS channel to output a serial bit stream of encoded PCI address and data information.
6. A computer, comprising:
an integrated central processing unit and graphics subsystem in a single chip;
a first Low Voltage Differential Signal (LVDS) channel directly extending from the integrated central processing unit and graphics subsystem, wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction;
a system memory directly coupled to the integrated central processing unit and graphics subsystem; and
a graphics memory directly coupled to the integrated central processing unit and graphics subsystem;
wherein the integrated central processing unit and graphics subsystem in a single chip directly conveys a serial bit stream of digital video information to a third differential signal channel.
7. The computer of claim 6 further comprising a connector adapted to convey a second LVDS channel comprising two unidirectional, differential signal pairs that transmit data in opposite directions.
8. The computer of claim 6 wherein the third differential signal channel conveys Transition Minimized Differential Signaling (TDMS) signals.
9. The computer of claim 6 wherein the first LVDS channel conveys encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form.
10. The computer of claim 7 wherein the second LVDS channel conveys encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form.
11. The computer of claim 7 wherein the second LVDS channel conveys Universal Serial Bus (USB) protocol signals.
12. A computer, comprising:
a central processing unit directly connected to a Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, differential signal pairs transmitting data in opposite directions:
a graphics controller coupled to the central processing unit to convey digital video information through a second differential signal channel conveying Transition Minimized Differential Signaling (TDMS) signals; and
a system memory directly connected to the central processing unit.
13. The computer of claim 12 wherein the central processing unit and the graphics controller are integrated in a single chip.
14. A computer, comprising:
an integrated central processing unit and graphics subsystem in a single chip directly connected to a first Low Voltage Differential Signal (LVDS) channel wherein the first LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction;
the integrated central processing unit and graphics subsystem directly connected to a second differential signal channel conveying Transition Minimized Differential Signaling (TDMS) digital video display signals.
15. The computer of claim 14 , further comprising a connector connected to a third LVDS channel comprising two unidirectional, differential signal pairs that transmit data in opposite directions.
16. The computer of claim 15 wherein the third LVDS channel conveys encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form.
17. The computer of claim 15 wherein the third LVDS channel conveys Universal Serial Bus (USB) protocol signals.