GaN HEMT power transistor pulse leveling circuit
View Patent ↗An apparatus comprising an RF circuit, a converter circuit, an amplifier, and a delay circuit. The RF circuit may be configured to generate (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal. The converter circuit may be configured to generate a second intermediate signal in response to the first intermediate signal. The amplifier may be configured to generate a third intermediate signal in response to the second intermediate signal. The delay circuit may be configured to generate the control signal in response to the third intermediate signal. The RF circuit may generate the output signal having a flattened response by providing pulse shaping in response to the control signal.
1. An apparatus comprising:
an RF circuit configured to generate (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal;
a converter circuit configured to generate a second intermediate signal in response to said first intermediate signal;
an amplifier configured to generate a third intermediate signal in response to the second intermediate signal; and
an RC delay circuit configured to generate said control signal in response to the third intermediate signal, wherein said RF circuit generates said output signal having a flattened response by providing pulse shaping in response to said control signal.
2. The apparatus according to claim 1 , wherein said RC delay circuit comprises a first resistor, a second resistor, and a capacitor, wherein said first resistor and said second resistor are sized to create said flattened response of said output signal.
3. The apparatus according to claim 1 , wherein said amplifier comprises a first operational amplifier and a second operational amplifier.
4. The apparatus according to claim 3 , wherein said first operational amplifier increases a gate voltage of a device under test.
5. The apparatus according to claim 3 , wherein said second operational amplifier buffers current to provide isolation.
6. The apparatus according to claim 1 , wherein said RF circuit comprises an RF matching circuit configured to test a GaN HEMT power transistor.
7. The apparatus according to claim 1 , wherein said RC delay circuit comprises one or more resistors and one or more capacitors.
8. An apparatus comprising:
means for generating (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal;
means for generating a second intermediate signal in response to said first intermediate signal;
means for generating a third intermediate signal in response to the second intermediate signal; and
means for generating said control signal using an RC delay circuit in response to the third intermediate signal, wherein said apparatus generates said output signal having a flattened response by providing pulse shaping in response to said control signal.
9. A method for leveling pulses in a signal generated by a GaN HEMT power transistor, comprising the steps of:
(A) generating (i) an output signal and (ii) a first intermediate signal, in response to (i) an input signal and (ii) a control signal;
(B) generating a second intermediate signal in response to said first intermediate signal;
(C) generating a third intermediate signal in response to the second intermediate signal; and
(D) generating said control signal in response to the third intermediate signal using an RC delay circuit, wherein said method generates said output signal having a flattened response by providing pulse shaping in response to said control signal.