Method and apparatus for limiting access to an integrated circuit (IC)
A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
1. A method comprising:
a) determining at an integrated circuit (IC) if a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit;
b) determining at the IC if the clock frequency is abnormal by virtue of being faster than a specified upper clock frequency limit;
c) determining at the IC if the clock frequency is abnormal by virtue of the clock signal having stopped;
utilizing at least one bandgap reference for the determining if the clock frequency is slower than the specified lower clock frequency limit and for determining if the clock frequency is faster than the specified upper clock frequency limit, wherein the utilizing the bandgap reference comprises utilizing a sampled bandgap reference, wherein the sampled bandgap reference is refreshed to maintain accuracy of the bandgap reference; and
limiting access to the IC in response to determining the clock frequency is abnormal by at least one of a), b), and c).
2. The method of claim 1 wherein the determining at the IC if the clock frequency of the clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit is independent of a duty cycle of the clock signal and wherein the determining at the IC if the clock frequency is abnormal by virtue of being faster than a specified upper clock frequency limit is independent of the duty cycle.
3. The method of claim 1 further comprising:
determining at the IC if a power supply voltage is abnormal by virtue of the power supply voltage being outside of a specified voltage range; and
limiting access to the IC in response to determining the power supply voltage is abnormal.
4. The method of claim 3 wherein determining at the IC if the power supply voltage is abnormal by virtue of the power supply voltage being outside of the specified voltage range comprises:
determining if the power supply voltage of the IC is lower than a lower power supply voltage limit; and
determining if the power supply voltage of the IC is higher than an upper power supply voltage limit.
5. The method of claim 3 further comprising:
determining at the IC if a temperature of the IC is abnormal by virtue of the temperature being outside of a specified temperature range; and
limiting access to the IC in response to determining the temperature of the IC is abnormal.
6. The method of claim 5 wherein determining at the IC if the temperature is abnormal by virtue of the temperature being outside of the specified temperature range comprises:
determining if the temperature of the IC is lower than a lower temperature limit; and
determining if the temperature of the IC is higher than an upper temperature limit.
7. The method of claim 1 wherein the determining at the IC if a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than the specified lower clock frequency limit, the determining at the IC if the clock frequency is abnormal by virtue of being faster than the specified upper clock frequency limit, and the determining at the IC if the clock frequency is abnormal by virtue of the clock signal having stopped occur contemporaneous with each other.
8. The method of claim 1 wherein the utilizing the bandgap reference consumes an average power of less than five microwatts.
9. The method of claim 1 wherein the limiting the access to the IC in response to determining the clock frequency is abnormal further comprises at least one of: inhibiting an external signal line of the IC, inhibiting execution of an instruction in the IC, resetting at least a portion of the IC, disabling reading of at least a portion of a memory array of the IC, and disabling execution of instructions stored in at least a portion of the memory array of the IC.
10. The method of claim 1 further comprising:
detecting whether the clock signal at the node is abnormal by virtue of the clock signal having a duty cycle that is outside of a specified duty cycle range.
11. The method of claim 1 further comprising:
detecting whether the clock signal at the node is abnormal by virtue of the clock signal being stopped at a low logic level.
12. The method of claim 1 further comprising:
detecting whether the clock signal at the node is abnormal by virtue of the clock signal being stopped at a high logic level.
13. The method of claim 1 wherein the utilizing the sampled bandgap reference comprises:
referencing the sampled bandgap reference for clock abnormality detection, for voltage detection, and for temperature detection.
14. An integrated circuit (IC) comprising:
a clock detector, the clock detector comprising:
a low clock frequency detector to detect if a clock signal at a node of the IC is abnormal by virtue of a frequency of the clock signal being below a specified lower limit;
a high clock frequency detector to detect if the clock signal at the node is abnormal by virtue of the frequency of the clock signal being above a specified upper limit;
at least one sampled bandgap reference for the determining if the frequency of the clock signal is below the specified lower limit and for determining if the frequency of the clock signal is above the specified upper limit, wherein the sampled bandgap reference is refreshed to maintain accuracy of the bandgap reference;
a stopped clock detector to detect if the clock signal at the node is abnormal by virtue of the clock signal being stopped; and
a tamper controller to limit access to the IC in response to determining the clock signal is abnormal.
15. The IC of claim 14 wherein the clock detector further comprises:
an abnormal duty cycle detector to detect if the clock signal at the node is abnormal by virtue of the clock signal having a duty cycle that is outside of a specified duty cycle range.
16. The IC of claim 14 wherein the stopped clock detector further comprises:
a clock stopped low detector to detect if the clock signal at the node is abnormal by virtue of the clock signal being stopped at a low logic level; and
a clock stopped high detector to detect if the clock signal at the node is abnormal by virtue of the clock signal being stopped at a high logic level.
17. The IC of claim 14 further comprising:
a voltage detector to detect if a power supply voltage is abnormal by virtue of the power supply voltage being outside of a specified power supply voltage range.
18. A method comprising:
a) determining at an integrated circuit (IC) if a clock frequency of a clock signal at the IC is abnormal by virtue of being slower than a specified lower clock frequency limit;
b) determining at the IC if the clock frequency is abnormal by virtue of being faster than a specified upper clock frequency limit;
c) determining at the IC if the clock frequency is abnormal by virtue of the clock signal having stopped;
utilizing at least one bandgap reference for the determining if the clock frequency is slower than the specified lower clock frequency limit and for determining if the clock frequency is faster than the specified upper clock frequency limit, wherein the utilizing the bandgap reference consumes an average power of less than five microwatts; and
limiting access to the IC in response to determining the clock frequency is abnormal by at least one of a), b), and c).