Monolithic transmit/receive module driver

1. An integrated circuit comprising:

a first circuit configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal, wherein the plurality of inputs can be received in parallel in a first mode and as a serial bit stream in a second mode; and

a second circuit configured to generate a plurality of outputs in response to a third control signal and a fourth control signal, wherein said second circuit comprises an output buffer circuit configured to generate two of said plurality of outputs as complementary signals and a number of open-drain transistors configured to present the remainder of the plurality of outputs.

2. The integrated circuit according to claim 1 , wherein said first circuit comprises a serial/parallel driver and said second circuit comprises a transmit/receive control module.

3. The integrated circuit according to claim 1 , wherein said number of open-drain transistors comprise NMOS field effect transistors.

4. The integrated circuit according to claim 1 , wherein said second circuit further comprises a number of voltage translators configured to generate inputs to said output buffer circuit and said number of open-drain transistors in response to a number of input signals.

5. The integrated circuit according to claim 4 , wherein said second circuit further comprises a transmit/receive logic circuit configured to generate the input signals to said voltage translators in response to said third and said fourth control signals.

6. The integrated circuit according to claim 5 , wherein said transmit/receive logic circuit comprises a look up table defining relationships between said plurality of outputs and said third and said fourth control signals.

7. The integrated circuit according to claim 1 , wherein said first circuit comprises:

an output buffer circuit configured to generate said plurality of complementary outputs based upon a number of parallel input signals;

a data latch configured to latch said number of parallel input signals in response to said second control signal; and

a voltage translator circuit configured to translate a voltage level of the number of parallel input signals between a supply voltage of said data latch and a supply voltage of said output buffer circuit.

8. The integrated circuit according to claim 1 , wherein said integrated circuit is configured to control a transmit/receive (T/R) module.

9. The integrated circuit according to claim 8 , wherein said transmit/receive module is part of a radar system.

10. The integrated circuit according to claim 1 , wherein said integrated circuit comprises a complimentary metal oxide semiconductor (CMOS) integrated circuit.

11. The integrated circuit according to claim 1 , wherein said integrated circuit is part of a radio frequency (RF) transmit/receive system.

12. A method of driving a transmit/receive module comprising the steps of:

generating a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal, wherein the plurality of inputs can be received in parallel in a first mode and as a serial bit stream in a second mode; and

generating a plurality of outputs in response to a third control signal and a fourth control signal, wherein two of said plurality of outputs are generated as complementary signals and a remainder of the plurality of outputs are generated using a number of open-drain transistors.

13. The method according to claim 12 , further comprising:

controlling one or more digital phase shifters with said plurality of complementary outputs.

14. The method according to claim 12 , further comprising:

controlling one or more digital attenuators with said plurality of complementary outputs.

15. The method according to claim 12 , further comprising:

controlling one or more digital phase shifters and one or more digital attenuators with said plurality of complementary outputs.

16. The method according to claim 12 , further comprising:

controlling one or more transmit/receive (T/R) switches with said plurality of outputs.

17. The method according to claim 12 , further comprising:

controlling one or more power amplifiers in a transmit path and one or more low noise amplifiers in a receive path in response to said third control signal and said fourth control signal.

18. The method according to claim 12 , further comprising:

separately controlling two or more power amplifier stages in a transmit path in response to said third control signal and said fourth control signal; and

separately controlling two or more low noise amplifier stages in a receive path in response to said third control signal and said fourth control signal.

19. The method according to claim 18 , further comprising:

controlling one or more transmit/receive switches in response to one or more of said third and said fourth control signals.

20. The method according to claim 12 , further comprising simultaneously controlling (i) one or more transmit/receive switches, (ii) one or more power amplifiers in a transmit path and (iii) one or more low noise amplifiers in a receive path based upon a logical combination of said third and said fourth control signals.

21. An integrated circuit comprising:

a first circuit configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal, wherein the plurality of inputs can be received in parallel in a first mode and as a serial bit stream in a second mode, and said first circuit comprises an output buffer circuit configured to generate said plurality of complementary outputs based upon a number of parallel input signals, a data latch configured to latch said number of parallel input signals in response to said second control signal, and a voltage translator circuit configured to translate a voltage level of the number of parallel input signals between a supply voltage of said data latch and a supply voltage of said output buffer circuit; and

a second circuit configured to generate a plurality of outputs in response to a third control signal and a fourth control signal.