Internal voltage generator and semiconductor memory device including the same
View Patent ↗A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.
1. An internal voltage generator circuit, comprising:
an internal voltage detector configured to detect the level of an internal voltage to output an activated pump enable signal when the level of the internal voltage is below a minimum value, the level of the internal voltage at which the pump enable signal is activated depending on operation speed information of a semiconductor device; and
an internal voltage pump configured to generate the internal voltage in response to the pump enable signal.
2. The internal voltage generator circuit of claim 1 , wherein the internal voltage comprises a negative voltage, and the internal voltage detector includes:
a plurality of pull-up transistors configured to receive a ground voltage through gates thereof to pull up a detection node whose level determines the activation/deactivation of the pump enable signal, and
a pull-down transistor configured to receive the negative voltage through a gate thereof to pull down the detection node,
wherein at least one of the pull-up transistors is turned off or on depending on the operation speed information.
3. The internal voltage generator circuit of claim 2 , wherein the internal voltage detector includes:
a pull-up transistor configured to receive a ground voltage through a gate thereof to pull up a detection node whose level determines the activation/deactivation of the pump enable signal, and
a plurality of pull-down transistors configured to receive the negative voltage through gates thereof to pull down the detection node,
wherein at least one of the pull-down transistors is turned off or on depending on the operation speed information.
4. The internal voltage generator circuit of claim 2 , wherein the internal voltage pump includes:
an oscillator configured to output a periodic signal in response to the pump enable signal,
a pump controller configured to output a pump control signal in response to the periodic signal, and
a charge pump configured to pump the negative voltage in response to the pump control signal.
5. The internal voltage generator circuit of claim 2 , wherein the internal voltage generator circuit is adapted for use in a semiconductor memory device, and the operation speed information includes CAS latency information.
6. The internal voltage generator circuit of claim 1 , wherein the internal voltage comprises a high voltage.
7. The internal voltage generator circuit of claim 6 , wherein the internal voltage detector includes:
a voltage divider configured to divide the high voltage to generate a feedback voltage, a division ratio of the high voltage depending on the operation speed information; and a comparator configured to compare the feedback voltage with a reference voltage to output the pump enable signal.
8. The internal voltage generator circuit of claim 7 , wherein the voltage divider includes a plurality of voltage divider units configured to divide the high voltage to generate the feedback voltage, and at least one of the voltage divider units is electrically shorted or opened depending on the operation speed information.
9. The internal voltage generator circuit of claim 6 , wherein the internal voltage pump includes
an oscillator configured to output a periodic signal in response to the pump enable signal,
a pump controller configured to output a pump control signal in response to the periodic signal, and
a charge pump configured to pump the high voltage in response to the pump control signal.
10. The internal voltage generator circuit of claim 6 , wherein the internal voltage generator circuit is adapted for use in a semiconductor memory device, and the operation speed information includes CAS latency information.