Variable impedance memory device biasing circuits and methods

1. An integrated circuit, comprising:

at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and

a biasing circuit comprising

a current source coupled to the shunt node configurable to provide a first current in a first type operation, and

a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein

in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC, and

the voltage regulator includes

a regulator amplifier having a first input coupled to a reference voltage and a second input coupled to the shunt node, and an amplifier output, and

a one-way current supply device coupled to the shunt node configured to provide current in one direction based on a signal from the amplifier output.

2. The integrated circuit of claim 1 , wherein:

the at least one PMC is coupled between a first power supply node and the shunt node and is configured to sink current from the shunt node in the first type operation; and

the current source is coupled between the shunt node and a second power supply node and configured to provide the first current to the shunt node, and

the voltage regulator is configured to shunt current from the shunt node and does not source current to the shunt node.

3. The integrated circuit of claim 1 , wherein:

the at least one PMC is coupled between a first power supply node and the shunt node and is configured to source current to the shunt node in the first type operation; and

the current source is coupled between the shunt node and a second power supply node and is configured to sink the first current from the shunt node, and

the voltage regulator is configured to source current to the shunt node and does not sink current from the shunt node.

4. The integrated circuit of claim 1 , wherein:

the current source is further configurable to provide a second current in a second type operation; wherein

the first type operation is a read operation and the second type operation is a program operation, and the first current is less than the second current.

5. The integrated circuit of claim 1 , wherein:

the current source includes a current source transistor having a current path coupled to the shunt node and a control terminal coupled to receive a bias signal that controls the amount of current flowing through the current source transistor.

6. The integrated circuit of claim 1 , further including:

a switch circuit that couples the PMC to a first voltage node in the first type operation, and to an erase voltage node in an erase operation; wherein

the current source is disabled in the erase operation, and

the voltage regulator is configured to provide current with respect to the shunt node in an opposite direction as a current flow of the at least one PMC in the erase operation.

7. The integrated circuit of claim 1 , further including:

a detect circuit coupled to the shunt node configured to activate a sense signal when a potential at the shunt node is outside of a predetermined limit.

8. An integrated circuit, comprising:

a plurality of memory cells, each including a memory element formed with a solid ion conductor material, and a select device that couples the memory element to a shunt node;

a voltage source that includes

an amplifier having a first input coupled to the shunt node, a second input coupled to receive a reference voltage, and an amplifier output, and

a regulating transistor having a source-drain path coupled between a first power supply voltage and the shunt node, and a gate coupled to the amplifier output; and

a current source circuit coupled between the shunt node and a second power supply voltage.

9. The integrated circuit of claim 8 , wherein:

the reference voltage has a first value in a read mode of operation that is less than a threshold voltage, and a second value in a program mode of operation that is greater than the threshold voltage; and

the current source circuit is configured to source a first current in the read mode and second current in the program mode; wherein

the threshold voltage is the voltage at which a memory element can be programmed from a high impedance state to a low impedance state, and the second current is greater than the first current.

10. The integrated circuit of claim 8 , wherein:

the regulating transistor is a p-type insulated gate field effect transistor, and the first power supply voltage is a high power supply voltage; and

the current source circuit includes an n-type insulated gate field effect transistor having a source-drain path coupled between the shunt node and a low power supply voltage.

11. The integrated circuit, of claim 8 , further including:

each memory cell having a first memory element coupled to the select device at a first terminal; and

a first switch element that selectively switches the second terminal of at least one memory element between the first power supply voltage and an erase voltage, less than the first power supply voltage.

12. The integrated circuit, of claim 11 , further including:

a second switch element that selectively switches the shunt node between the current source circuit and the second power supply voltage.

13. The integrated circuit, of claim 8 , further including:

an output section configured to generate an indication in response to the regulating transistor drawing a predetermined amount of current.