Deep trench capacitor

1. A method of forming a deep trench capacitor in a semiconductor-on-insulator (SOI) substrate, wherein the deep trench capacitor is formed prior to forming the SOI substrate, the method comprising:

providing a pad layer positioned above a bulk substrate;

etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, the deep trench having a sidewall and a bottom;

doping a portion of the bulk substrate located along the sidewall and the bottom of the deep trench to form a buried plate, the buried plate being conductive;

depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench; and

removing the pad layer selective to the node dielectric and the dielectric cap such that a portion of the deep trench capacitor including an exposed portion of the node dielectric extends above a top surface of the bulk substrate followed by growing an insulator layer directly on top of the bulk substrate, and growing a SOI layer on top of the insulator layer.

2. The method of claim 1 , wherein forming the buried plate comprises heavily doping the portion of the bulk substrate using a blanket doping technique, wherein the pad layer protects a top surface of the bulk substrate from diffusion of unwanted dopants.

3. The method of claim 1 , wherein growing the insulator layer comprises epitaxially growing a rare earth oxide comprising a thickness ranging from about 5 nm to about 500 nm.

4. The method of claim 1 , wherein growing the SOI layer comprises epitaxially growing a film comprising a thickness ranging from about 3 nm to about 10 nm.

5. The method of claim 1 , further comprising:

forming a semiconductor device adjacent to the deep trench capacitor; and

forming an electrical connection between a source or drain region of the semiconductor device and the inner electrode of the deep trench capacitor,

wherein the first semiconductor device and the deep trench capacitor together form a memory cell.

6. The method of claim 5 , wherein forming the electrical connection comprises forming a contact extending from a top surface of an inter-dielectric layer to the source or drain region of the semiconductor device and the inner electrode of the deep trench capacitor.

7. The method of claim 5 , further comprising:

forming a logic device adjacent to the semiconductor device.

8. The method of claim 1 , wherein a combined thickness of both the insulator layer and the SOI layer is equal to or less than a thickness of the pad nitride layer.

9. A method of forming a deep trench capacitor in a semiconductor-on-insulator (SOI) substrate, wherein the deep trench capacitor is formed prior to forming the SOI substrate, the method comprising:

providing a pad layer positioned above a bulk substrate;

etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, the deep trench having a sidewall and a bottom;

doping a portion of the bulk substrate located along the sidewall and the bottom of the deep trench to form a buried plate, the buried plate being conductive;

depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench; and

removing the pad layer selective to the node dielectric and the dielectric cap followed by growing an insulator layer directly on top of the bulk substrate, and growing a SOI layer on top of the insulator layer,

wherein a portion of the deep trench capacitor including an exposed portion of the node dielectric extends above a top surface of the insulator layer.

10. The method of claim 9 , further comprising:

forming a dielectric isolation region separating the node dielectric from the SOI layer and separating the node dielectric from at least a portion of the insulator layer.

11. The method of claim 9 , wherein the portion of the node dielectric extending above the insulator layer is separated from the SOI layer by a space.

12. The method of claim 9 , wherein a combined thickness of both the insulator layer and the SOI layer is equal to or less than a thickness of the pad nitride layer.

13. The method of claim 9 , wherein a top surface of the SOI layer is substantially flush with a top surface of the deep trench capacitor.

14. The method of claim 9 , wherein growing the insulator layer and growing the SOI layer forms a space between the exposed portion of the node dielectric extending above the insulator layer and both the insulator layer and the SOI layer, the space gradually increasing in width as a distance above the top surface of the bulk substrate increases.