SiGe HBT and method of manufacturing the same
A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.
1. A method of manufacturing SiGe HBT (Heterojunction Bipolar Transistors), comprising the following steps in the sequence set forth:
forming shallow trenches in a silicon substrate;
forming a pseudo buried layer at a bottom of each of the shallow trenches;
filling an oxide into each of the shallow trenches to form shallow trench field oxides;
forming a polysilicon gate with a thickness of greater than 150 nm above each of the shallow trench field oxides;
forming a collector region beneath a surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers;
forming a base region by growing a SiGe epitaxial layer on the polysilicon gates and the collector region;
forming emitter region isolation oxides on a part of the base region on the collector region;
forming an emitter region on the emitter region isolation oxides and a part of the base region.
2. The method according to claim 1 , further comprising forming spacers on sidewalls of the emitter region and the emitter region isolation oxides.
3. The method according to claim 1 , further comprising forming deep contact holes for picking up the collector region, each of the deep contact holes being formed through the shallow trench field oxides and connecting to the respective pseudo buried layer.
4. The method according to claim 1 , further comprising forming contact holes for picking up the base region and the emitter region, the contact holes being formed on the base region and the emitter region, respectively.
5. The method according to claim 1 , wherein the polysilicon gates are formed by using gate polysilicon process of a MOSFET in a CMOS process.
6. The method according to claim 1 , wherein the pseudo buried layer is formed by N-type heavily doped ion implantation; the impurity implanted is phosphorus; a dose of the implantation is from 1 e 14 cm −2 to 1 e 16 cm −2 ; and an energy of the implantation is from 2 KeV to 50 KeV.
7. The method according to claim 1 , wherein the collector region is formed by N-type ion implantation; the impurity implanted is phosphorus; a dose of the implantation is from 1 e 12 cm −2 to 5 e 14 cm −2 ; and an energy of the implantation is from 20 KeV to 350 KeV.
8. The method according to claim 7 , wherein the emitter region is formed by an N-doped polysilicon; the N-type impurity doped is phosphorus or arsenic; a dose of the doping is greater than 1 e 15 cm −2 .
9. The method according to claim 1 , wherein the SiGe epitaxial layer has a thickness less than or equal to 1000 Å.
10. The method according to claim 1 , further comprising performing P-type doping to a part of the SiGe epitaxial layer not covered by the emitter region; the P-type impurity is boron or boron fluoride; a dose of the doping is greater than 1 e 15 cm −2 .