High power semiconductor package subsystems
A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect.
1. A method for packaging an electronic device assembly, the method comprising:
providing a power device die for incorporation in a packaged electronic device assembly;
providing a metallic coin for incorporation in the packaged electronic device assembly and configured for incorporation in a package substrate;
coupling a first major surface of the power device die to a first major surface of the metallic coin, wherein the metallic coin is formed prior to said coupling;
embedding the metallic coin into the package substrate, wherein
said embedding is performed subsequent to said coupling,
said embedding comprises inserting the metallic coin into a hole provided in the package substrate, and
the package substrate is preformed;
adhesively coupling one or more device die to a first major surface of the package substrate, wherein
a second major surface of the metallic coin opposite the first major surface of the metallic coin is accessible at a second major surface of the package substrate, and
the second major surface of the package substrate is opposite the first major surface of the package substrate; and
electrically coupling the power device die to a device die of the one or more device die.
2. The method of claim 1 , wherein
said coupling the first major surface of the power device die to the first major surface of the metallic coin comprises using a metallurgical die attach process providing a low thermal or electrical resistance.
3. The method of claim 2 wherein the metallurgical die attach process comprises one of a AuSi, AuSn, or Ag die attach process.
4. The method of claim 1 wherein the metallic coin comprises a copper coin.
5. The method of claim 1 wherein said electrically coupling the power device die to the device die of the one or more device die comprises:
forming a wire bond from a power device die signal pad to an electrical contact not on the power device die, wherein
a second major surface of the power device die comprises one or more signal pads,
the second major surface of the power device die is opposite the first major surface of the power device die, and
the electrical contact not on the power device die is located on one of the package substrate or the device die.
6. The method of claim 5 wherein the package substrate is a printed circuit board and the electrical contact not on the power device die is coupled to a trace of the printed circuit board.
7. The method of claim 5 further comprising:
forming an encapsulant over and around sides of the power device die, the one or more device die, the wire bonds, and over the package substrate.
8. The method of claim 5 further comprising:
providing the package substrate in an air cavity package.
9. The method of claim 1 wherein said electrically coupling the power device die to the device die of the one or more device die comprises:
forming a planarization layer over the package substrate and over and around the power device die and the one or more device die, wherein the planarization layer is a dielectric layer;
forming a first patterned metallization layer for a package interconnect over the planarization layer, wherein
the first patterned metallization layer is electrically coupled with a power device die signal pad through a via formed in the planarization layer,
the first patterned metallization layer is electrically coupled with a device die signal pad through a via formed in the planarization layer, and
a second major surface of the power device die comprises one or more signal pads; and
forming the package interconnect over the first patterned metallization layer from one or more dielectric layers and one or more additional patterned metallization layers.
10. The method of claim 9 , wherein
the power device die comprises one or more substantially similar unit cells, and
each of the one or more unit cells comprises a power transistor and a plurality of signal contacts.