Method for manufacturing semiconductor device
View Patent ↗A method of fabricating a semiconductor component that including the following steps is provided. A plurality of stacked structures is formed on a substrate. A first dielectric layer is formed to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures. A dry conformable etching process is performed to conformably remove the first dielectric layer until a portion of the first dielectric layer located outside of the overhangs is removed. A second dielectric layer is formed on the stacked structures, wherein the second dielectric layer connects the adjacent overhangs to form an air gap between the stacked structures.
1. A method of fabricating a semiconductor device, comprising:
forming a plurality of stacked structures on a substrate;
forming a first dielectric layer to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures;
performing a dry conformable etching process to conformably remove the first dielectric layer until all portions of the first dielectric layer outside of the overhangs and along the sidewalls of the stacked structures are completely removed; and
forming a second dielectric layer on the stacked structures, wherein the second dielectric layer connects the adjacent overhangs to form an air gap between the stacked structures.
2. The method of fabricating the semiconductor device of claim 1 , further comprising forming a liner layer to cover the stacked structures after the stacked structures are formed.
3. The method of fabricating the semiconductor device of claim 2 , wherein an etching rate of the liner layer is smaller than an etching rate of the first dielectric layer during the dry conformable etching process.
4. The method of fabricating the semiconductor device of claim 1 , wherein the dry conformable etching process comprises an isotropic etching process.
5. The method of fabricating the semiconductor device of claim 4 , wherein the dry conformable etching process comprises a non-plasma etching process or a plasma etching process.
6. The method of fabricating the semiconductor device of claim 1 , wherein the dry conformable etching process comprises a gas etching process.
7. The method of fabricating the semiconductor device of claim 6 , wherein the dry conformable etching process is adapted for a line width of less than or equal to 50 nanometers.
8. The method of fabricating the semiconductor device of claim 1 , wherein a ratio of a sectional area of the air gap to a sectional area of a space between the stacked structures is higher than 70% and less than or equal to 90%.
9. The method of fabricating the semiconductor device of claim 1 , wherein when the semiconductor device is a non-volatile memory, each of the stacked structures successively comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate from bottom to top.
10. The method of fabricating the semiconductor device of claim 9 , wherein the dry conformable etching process comprises: removing a portion of the first dielectric layer located below or equal to a height of a top portion of each of the control gates.
11. The method of fabricating the semiconductor device of claim 9 , wherein a lower width of the air gap is larger than or equal to an upper width of the air gap between the floating gates.
12. The method of fabricating the semiconductor device of claim 9 , wherein each of the stacked structures further comprises a conductor layer, disposed on each of the control gates.
13. The method of fabricating the semiconductor device of claim 1 , wherein each of the stacked structures further comprises a cap layer, the cap layer is an uppermost layer of the stacked structure.
14. The method of fabricating the semiconductor device of claim 13 , wherein the dry conformable etching process comprises removing a portion of the first dielectric layer located below or equal to a height of the bottom portion of the cap layer.