Method, system and device for recessed contact in memory array
Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.
1. A memory device, comprising:
an array of memory cells each comprising a selector transistor, the array including a word-line contact region in a base component in substantially direct contact with an electrically conductive interconnect electrically coupled to a word-line electrode, the word-line contact region positioned between memory cells of the array,
wherein the word-line contact region has a width between a pair of selector transistors of the array that is greater than two times a width of each of the selector transistors.
2. The memory device of claim 1 , further comprising trenches having a depth to insulate select transistors of adjacent memory cells, wherein the word-line contact region has a depth substantially the same as the depth of the trenches.
3. The memory device of claim 1 , wherein the selector transistors comprise bipolar junction transistors.
4. A memory device, comprising:
an array of memory cells each comprising a selector transistor, the array including a word-line contact region in a base component in substantially direct contact with an electrically conductive interconnect electrically coupled to a word-line electrode, the word-line contact region positioned between memory cells of the array,
wherein the selector transistors are regularly spaced along a word-line direction in accordance with a pitch multiplication pattern on either side of the word-line contact region, and the word-line contact region represents an interruption of the pitch multiplication pattern.
5. The memory device of claim 4 , wherein the word-line contact region has a width between a pair of selector transistors of the array that is greater than two times a width of each of the selector transistors.
6. The memory device of claim 5 , wherein the width of the word-line contact region is greater than four times a width of each of the selector transistors.
7. A memory device, comprising:
an array of memory cells each comprising a selector transistor, the array including a word-line contact region in a base component in substantially direct contact with an electrically conductive interconnect electrically coupled to a word-line electrode, the word-line contact region positioned between memory cells of the array,
wherein the base component comprises a cathode component common to a plurality of the selector transistors.
8. A memory device, comprising:
an array of memory cells each comprising a selector transistor, the array including a word-line contact region in a base component in substantially direct contact with an electrically conductive interconnect electrically coupled to a word-line electrode, the word-line contact region positioned between memory cells of the array,
wherein each selector transistor further comprises an emitter component electrically coupled to the base component, wherein the word-line contact region is recessed relative to the emitters.
9. The memory device of claim 8 , wherein each memory cell of the array of memory cells comprises a phase change memory storage element electrically coupled between the emitter and a bit-line electrode.
10. The memory device of claim 9 , wherein the word-line contact region has a width between a pair of emitters greater than four times a width of the phase change memory storage component in each memory cell.
11. A method, comprising:
energizing an electrode of a memory array to energize one or more selector transistors of the memory array by way of an electrically conductive interconnect in substantially direct contact with a recessed contact region formed in a cathode material of the one or more selector transistors, and to energize one or more phase change material storage cells electrically connected to the one or more selector transistors as part of a programming operation,
wherein emitters of the selector transistors are regularly spaced along a word-line direction in accordance with a pitch multiplication pattern on either side of the recessed word-line contact region, and the word-line contact region represents an interruption of the pitch multiplication pattern.
12. The memory device of claim 11 , wherein the word-line contact region has a width between a pair of selector transistors of the array that is greater than two times a width of each of the selector transistors.