Safeguarding data through an SMT process
View Patent ↗Structures and methods for recovering data in a semiconductor memory device are disclosed herein. In one embodiment, a method of recovering data in a semiconductor memory device, can include: (i) pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell; (ii) storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state; (iii) mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and (iv) performing a recovery of the first data state by reducing the resistance of the first memory cell.
1. A method of recovering data in a semiconductor memory device, the method comprising:
a) pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell;
b) storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state;
c) mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and
d) performing a recovery of the first data state by reducing the resistance of the first memory cell.
2. The method of claim 1 , wherein each of the first and second memory cells comprises a programmable metallization cell (PMC).
3. The method of claim 1 , wherein the high temperature process comprises a surface-mount technology (SMT).
4. The method of claim 1 , wherein the performing the recovery is initiated by a command received by the semiconductor memory device.
5. The method of claim 1 , wherein the performing the recovery comprises performing a refresh on the first and second memory cells.
6. The method of claim 5 , wherein the performing the refresh on the first and second memory cells comprises using a program voltage that is less than the formation voltage.
7. The method of claim 1 , wherein the performing the recovery comprises performing differential sensing on the first and second memory cells.
8. The method of claim 1 , wherein the performing the recovery comprises performing differential sensing and a refresh on the first and second memory cells.
9. The method of claim 1 , wherein the performing the recovery comprises determining a type of recovery process to be performed, wherein the type comprises at least one of refresh, differential sensing, and a combination of differential sensing and refresh.
10. The method of claim 1 , wherein each of the first and second memory cells comprises:
a) a programmable impedance element having an active electrode coupled to a bit line; and
b) a transistor having a drain coupled to the inert electrode of the programmable impedance element, a gate coupled to a word line, and a source coupled to a source line.
11. The method of claim 1 , wherein each of the first and second memory cells comprises a programmable impedance element having:
a) an inert electrode coupled to a first side of a solid electrolyte;
b) an active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and
c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.
12. The method of claim 11 , wherein the conductive path in the programmable impedance element is formed by application of a first voltage across the active and inert electrodes, the conductive path substantially remaining once formed after the first voltage is removed.
13. The method of claim 11 , wherein at least a portion of the conductive path is dissolved to erase the programmable impedance element by application of a second voltage across the active and inert electrodes.
14. The method of claim 1 , wherein the formation voltage is in a range of from about 2.5 V to about 3 V.
15. The method of claim 1 , wherein the performing the recovery comprises using a program voltage in a range of from about 1 V to about 1.5 V.
16. The method of claim 1 , wherein the high temperature process comprises a process of at least 250° C.
17. The method of claim 1 , further comprising packaging the semiconductor memory device prior to the mounting on the PCB.
18. The method of claim 17 , wherein the pre-conditioning the first memory cell occurs prior to the packaging.
19. The method of claim 17 , wherein the pre-conditioning the first memory cell occurs after the packaging.
20. An apparatus for recovering data in a semiconductor memory device, the apparatus comprising:
a) means for pre-conditioning a first memory cell on the semiconductor memory device by using a formation voltage to program a first data state in the first memory cell;
b) means for storing a second data state in a second memory cell on the semiconductor memory device by maintaining the second memory cell in a virgin state;
c) means for mounting the semiconductor memory device on a printed-circuit board (PCB) by using a high temperature process that increases a resistance of the first memory cell; and
d) means for performing a recovery of the first data state by reducing the resistance of the first memory cell.