IP Library Granted Patent US 9,006,639
Granted Patent B2
US 9,006,639 · App. 13/642,101 · Granted Apr 14, 2015

Pixel architecture with the control terminal of a first switch coupled to the control terminal of a second switch and method

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Quick Facts
Patent No.
US 9,006,639
App. No.
13/642,101
Granted
Apr 14, 2015
Kind
B2
Abstract

In accordance with an embodiment, a pixel includes at least two switches, each switch having a control terminal and first and second current carrying terminals. The control terminals of the first and second switches are commonly connected together. In accordance with another embodiment, a method for transferring charge from a first switch to a capacitance includes applying voltage to the commonly connected control terminals of the first and second switches.

Claims (25)

1. A pixel, comprising:

a reset transistor having a control electrode and first and second current carrying electrodes;

a transfer transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode of the transfer transistor is coupled to the control electrode of the reset transistor, and the first current carrying conductor of the transfer transistor is coupled to the second current carrying transistor of the reset transistor and forms a first node.

2. The pixel of claim 1 , further including a source follower transistor having a control electrode and first and second current carrying electrodes, wherein the control electrode is coupled to the first current carrying electrode of the transfer transistor and to the second current carrying electrode of the reset transistor.

3. The pixel of claim 2 , wherein the first current carrying electrode of the reset transistor and the first current carrying electrode of the source follower transistor are coupled for receiving a first source of operating potential.

4. The pixel of claim 2 , wherein the first current carrying electrode of the reset transistor is coupled for receiving a first source of operating potential and the first current carrying electrode of the source follower transistor is coupled for receiving a second source of operating potential.

5. The pixel of claim 1 , further including a select transistor having a control electrode and first and second current carrying electrodes, the first current carrying electrode coupled to the second current carrying electrode of the source follower transistor.

6. The pixel of claim 1 , further including a pinned photodiode coupled to the second current carrying conductor of the transfer transistor.

7. The pixel of claim 1 , further including a floating diffusion capacitor coupled to the first node.

8. A pixel, comprising:

a photodiode having an anode and a cathode;

a first switch having a control terminal and first and second current carrying terminals, the first current carrying terminal coupled to the cathode of the photodiode;

a second switch having a control terminal and first and second current carrying terminals, the first current carrying terminal of the second switch coupled for receiving a first source of operating potential, the second current carrying terminal of the second switch coupled to the second current carrying terminal of the first switch, and the control terminal of the second switch coupled to the control terminal of the first switch;

a third switch having a control terminal and first and second current carrying terminals, the first current carrying terminal of the third switch coupled to the second current carrying terminals of the first and second switches;

an amplifier having an input coupled to the second current carrying terminal of the third switch; and

a memory element coupled to the second current carrying terminal of the first switch.

9. The pixel of claim 8 , wherein the memory element is a floating diffusion capacitor.

10. The pixel of claim 8 , wherein the amplifier is a transistor configured as a source follower.

11. The pixel of claim 8 , wherein the first, second, and third switches are comprised of first, second, and third transistors, respectively.

12. A method, comprising:

providing the plurality of pixels, wherein pixels of the plurality of pixels each include first, second, third, and fourth transistors, a photodiode, and a floating diffusion capacitor, wherein each transistor has a control electrode and first and second current carrying electrodes, the control electrodes of the first and second transistors commonly coupled together, the first current carrying electrode of the second transistor coupled to the second current carrying electrode of the first transistor and to the control electrode of the third transistor, and the second current carrying electrode of the third transistor coupled to the first current carrying electrode of the fourth transistor, the photodiode coupled to the second current carrying electrode of the second transistor, and the floating diffusion capacitor coupled to the second current carrying electrode of the first transistor;

resetting the photodiode and the floating diffusion capacitor by applying a first voltage that is greater than a first voltage level to the commonly connected control electrodes of the first and second transistors; and

transferring charge from the photodiode to the floating diffusion capacitance by applying a second voltage that is less than the first voltage level to the commonly connected control electrodes of the first and second transistors.

13. The method of claim 12 , further including coupling the first current carrying electrode of the first transistor for receiving a first source of operating potential and wherein the first voltage level is greater than a voltage level of the first source of operating potential.

14. The method of claim 13 , wherein the second voltage has a level that is less than the first voltage level and greater than a pinning voltage of the photodiode.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2012
From: DE WIT, YANNICK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 029337/0125 →