Method of inserting dummy patterns
View Patent ↗A method of inserting dummy patterns is provided. The method includes: determining an applicable area in which dummy patterns shall be inserted and an inapplicable area in which dummy patterns shall not be inserted on a chip; and inserting dummy patterns starting from one side of the inapplicable area and arranging the inserted dummy patterns into circles. The method of the present invention ensures that dummy patters are preferentially inserted around the device that requires protection by dummy patterns, so that good uniformity of chip pattern densities is guaranteed and within-wafer uniformity is improved, thus improving the yield and performance of semiconductor devices.
1. A method of inserting dummy patterns in an integrated circuit on a chip to improve within-wafer uniformity, the method comprising:
determining an applicable area of a chip in which dummy patterns shall be inserted;
determining at least one inapplicable area of the chip in which dummy patterns shall not be inserted, each of the at least one inapplicable areas surrounded by the applicable area; and
inserting dummy patterns on the chip starting at least at a first position in the applicable area, the first position adjacent to a first side of a first inapplicable area, wherein the dummy patterns are inserted equidistantly at a constant interval in a circlewise arrangement around the first inapplicable area, thereby improving within-wafer uniformity.
2. The method according to claim 1 , wherein the chip includes only one inapplicable area.
3. The method according to claim 1 , wherein the chip includes two inapplicable areas having a perpendicular distance provided between the first side of the first inapplicable area and a first side of a second inapplicable area, the first side of the first inapplicable area and the first side of the second inapplicable area facing each other;
wherein, if the perpendicular distance can accommodate an even number of dummy patterns, a first dummy pattern is inserted equidistantly at a constant interval in a circlewise arrangement around the first inapplicable area starting at the first position in the applicable area adjacent to the first side of the first inapplicable area, and a second dummy pattern is inserted equidistantly at a constant interval in a circlewise arrangement around the second inapplicable area starting at a second position in the applicable area adjacent to the first side of the second inapplicable area.
4. The method according to claim 1 , wherein the chip includes two inapplicable areas having a perpendicular distance provided between the first side of the first inapplicable area and a first side of a second inapplicable area, the first side of the first inapplicable area and the first side of the second inapplicable area facing each other;
wherein, if the shortest perpendicular distance can accommodate an odd number of dummy patterns, a first dummy pattern is inserted equidistantly at a constant interval in a circlewise arrangement around the first inapplicable area starting at the first position in the applicable area adjacent to the first side of the first inapplicable area, a second dummy pattern is inserted equidistantly at a constant interval in a circlewise arrangement around the second inapplicable area starting at a second point in the applicable area adjacent to the first side of the second inapplicable area, and a middle one of the odd number of dummy patterns is inserted arranged on a central line positioned in the applicable area between the first side of the first inapplicable area and the first side of the second inapplicable area.
5. The method according to claim 1 , wherein the applicable area and the at least one inapplicable area are each determined by using an Electronic Design Automation Tool and the dummy patterns are inserted by using the Electronic Design Automation tool.