Trap rich layer with through-silicon-vias in semiconductor devices
View Patent ↗An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.
1. A method comprising:
forming a circuit layer for an integrated circuit chip;
forming a trap rich layer above the circuit layer; and
forming through-semiconductor-vias above the circuit layer;
wherein the trap rich layer remains in a final structure for the integrated circuit chip.
2. The method of claim 1 , further comprising:
forming through-semiconductor-vias through the trap rich layer.
3. The method of claim 1 , further comprising:
forming the trap rich layer to surround the through-semiconductor-vias, except at top and bottom ends thereof.
4. The method of claim 1 , further comprising:
forming the circuit layer in a wafer;
forming the trap rich layer and the through-semiconductor-vias in a semiconductor substrate; and
bonding the semiconductor substrate to the wafer.
5. The method of claim 4 , wherein the forming of the trap rich layer and the through-semiconductor-vias in the semiconductor substrate further comprises:
forming holes for the through-semiconductor vias in the semiconductor substrate;
forming the trap rich layer at a surface of the semiconductor substrate, including a surface within the holes; and
filling the holes with an electrically conductive material for the through-semiconductor-vias.
6. The method of claim 4 , further comprising:
after bonding the semiconductor substrate to the wafer, removing a portion of the semiconductor substrate to expose an electrically conductive material of the through-semiconductor-vias.
7. The method of claim 6 , further comprising:
forming a second trap rich layer at exposed semiconductor material of the semiconductor substrate.
8. The method of claim 4 , further comprising:
forming a second circuit layer in a second wafer; and
bonding the second wafer to the semiconductor substrate.
9. The method of claim 4 , further comprising:
forming a second circuit layer on the semiconductor substrate, the trap rich layer and the through-semiconductor-vias being between the first and second circuit layers, and the through-semiconductor-vias electrically connecting the first and second circuit layers.
10. A method comprising: forming a trap rich layer in a semiconductor wafer; providing a circuit layer; and forming through-semiconductor-vias in the semiconductor wafer; wherein said trap rich layer is located above the circuit layer.
11. The method of claim 10 , further comprising:
forming the circuit layer in a first wafer;
bonding the semiconductor wafer to the first wafer such that the through-semiconductor-vias are in electrical contact with the circuit layer;
forming a second circuit layer for the integrated circuit chip in a second wafer; and
bonding the second wafer to the semiconductor wafer with the through-semiconductor-vias in electrical contact with the second circuit layer.
12. The method of claim 10 , further comprising:
forming holes into the semiconductor wafer for the through-semiconductor-vias;
forming the trap rich layer at a surface of the semiconductor wafer, including a surface within the holes; and
filling the holes with an electrically conductive material for the through-semiconductor-vias.
13. The method of claim 10 , further comprising:
forming the circuit layer in the semiconductor wafer.
14. The method of claim 13 , further comprising:
bonding the semiconductor wafer to another wafer having a second circuit layer therein;
and wherein the through-semiconductor-vias electrically connect the circuit layer to the second circuit layer.
15. The method of claim 13 , further comprising:
forming the through-semiconductor-vias through a semiconductor substrate layer within the semiconductor wafer;
forming the trap rich layer between the through-semiconductor-vias and a semiconductor material of the semiconductor substrate layer; and
forming at least one additional trap rich layer above or below the semiconductor substrate layer.
16. An integrated circuit chip comprising:
a circuit layer;
a trap rich layer located above the circuit layer; and
through-semiconductor-vias located above the circuit layer and in electrical contact with the circuit layer.
17. The integrated circuit chip of claim 16 , wherein:
the trap rich layer surrounds the through-semiconductor-vias, except at top and bottom ends thereof.
18. The integrated circuit chip of claim 16 , further comprising:
a semiconductor wafer containing the circuit layer; and
a semiconductor substrate containing the trap rich layer and the through-semiconductor-vias, the semiconductor substrate being bonded to the semiconductor wafer.
19. The integrated circuit chip of claim 18 , further comprising:
holes formed into the semiconductor substrate;
and wherein:
the trap rich is formed at a surface of the semiconductor substrate, including a surface within the holes; and
the through-semiconductor-vias comprise an electrically conductive material that fills the holes.