Pseudo tester-per-site functionality on natively tester-per-pin automatic test equipment for semiconductor test
View Patent ↗A system and method for testing devices are presented. Embodiments of the present invention use a central controller to coordinate the testing of a plurality of devices under test as well as a plurality of channel circuits that are each operable to be coupled to at least one I/O pin of a device under test of the aforementioned plurality of devices under test. Also, embodiments of the present invention include a plurality of intermediate processors that are each coupled to the central controller and operable to receive and send control signals. These intermediate processors are each coupled to a different set of channel circuits of the plurality of channel circuits and are operable to execute their own instantiation of a test program that is independent of any other intermediate processor of the plurality of intermediate processors for the testing of a device under test associated therewith.
1. A tester system comprising:
a central controller for coordinating testing of a plurality of devices under test;
a plurality of channel circuits, each channel circuit operable to be coupled to at least one I/O pin of a device under test of said plurality of devices under test; and
a plurality of intermediate processors each coupled to said central controller and each operable to receive control signals therefrom and operable to send control signals thereto, wherein further, each intermediate processor is coupled to a different set of channel circuits of said plurality of channel circuits and wherein each intermediate processor is operable to execute a respective test program independent of any other intermediate processor of said plurality of intermediate processors for the testing of a device under test associated therewith.
2. A tester system as described in claim 1 wherein each intermediate processor of said plurality of intermediate processors is operable to execute a respective instantiation of a test program for application to an associated device under test using an associated set of channel circuits coupled thereto.
3. A test system as described in claim 2 wherein a first set of said plurality of intermediate processors respectively execute a first test program for testing a first set of devices under test in lock step execution and wherein a second set of said plurality of intermediate processors respectively execute a second test program for testing a second set of devices under test and wherein further said second test program is different from and independent of said first test program.
4. A tester system as described in claim 1 wherein each of said plurality of intermediate processors is an embedded processor.
5. A test system as described in claim 1 wherein said plurality of channel circuits comprise:
clock pin channel circuits;
analog input channel circuits;
analog output channel circuits; and
digital input/output channel circuits.
6. A test system as described in claim 1 wherein each intermediate processor of said plurality of intermediate processors is coupled to independently receive respective vector data from said central controller.
7. A test system as described in claim 1 wherein said central controller is a tester workstation.
8. A method for testing a plurality of devices under test, comprising:
coordinating testing of a plurality of devices under test using a central controller;
coupling a plurality of channel circuits to at least one I/O pin of a device under test of said plurality of devices under test, wherein each channel circuit is operable to be coupled to at least one I/O pin of a device under test of said plurality of devices under test;
associating a plurality of intermediate processors, each operable to receive control signals therefrom and operable to send control signals thereto, to said central controller, wherein said central controller is operable to monitor an operational status of said plurality of channel circuits;
associating each intermediate processor of said plurality of intermediate processors to a different set of channel circuits of said plurality of channel circuits and wherein each intermediate processor is operable to execute a respective test program independent of any other intermediate processor of said plurality of intermediate processors for the testing of a device under test associated therewith.
9. A method for testing a plurality of devices under test as described in claim 8 wherein each intermediate processor of said plurality of intermediate processors is operable to execute a respective instantiation of a test program for application to an associated device under test using an associated set of channel circuits coupled thereto.
10. A method for testing a plurality of devices under test as described in claim 9 wherein a first set of said plurality of intermediate processors is operable to respectively execute a first test program for testing a first set of devices under test in lock step execution and wherein a second set of said plurality of intermediate processors is operable to respectively execute a second test program for testing a second set of devices under test and wherein further said second test program is different from and independent of said first test program.
11. A method for testing a plurality of devices under test as described in claim 8 wherein each of said plurality of intermediate processors is an embedded processor.
12. A method for testing a plurality of devices under test as described in claim 8 wherein said plurality of channel circuits comprise:
clock pin channel circuits;
analog input channel circuits;
analog output channel circuits; and
digital input/output channel circuits.
13. A method for testing a plurality of devices under test as described in claim 8 wherein each intermediate processor of said plurality of intermediate processors is coupled to receive respective vector data from said central controller.
14. A method for testing a plurality of devices under test as described in claim 8 wherein said central controller is a tester workstation.
15. A tester system comprising:
a central controller for coordinating testing of a plurality of devices under test;
a plurality of channel circuits, each channel circuit operable to be communicatively coupled to at least one I/O pin of a device under test of said plurality of devices under test; and
a plurality of intermediate processors each communicatively coupled to said central controller and each operable to receive control signals therefrom and operable to send control signals thereto, wherein further, each intermediate processor is communicatively coupled to a different set of channel circuits of said plurality of channel circuits and wherein each intermediate processor is operable to execute a set of instructions of a respective instantiation of a test program concurrently for the testing of a device under test associated therewith.
16. A tester system as described in claim 15 wherein each intermediate processor of said plurality of intermediate processors is operable to execute a respective instantiation of a test program for application to an associated device under test using an associated set of channel circuits coupled thereto.
17. A test system as described in claim 16 wherein a first set of said plurality of intermediate processors is operable to respectively execute a first test program for testing a first set of devices under test in lock step execution and wherein a second set of said plurality of intermediate processors is operable to respectively execute a second test program for testing a second set of devices under test and wherein further said second test program is different from and independent of said first test program.
18. A tester system as described in claim 15 wherein each of said plurality of intermediate processors is an embedded processor.
19. A test system as described in claim 15 wherein said plurality of channel circuits comprise:
clock pin channel circuits;
analog input channel circuits;
analog output channel circuits; and
digital input/output channel circuits.
20. A test system as described in claim 15 wherein each intermediate processor of said plurality of intermediate processors is coupled to receive respective vector data from said central controller.
21. A test system as described in claim 15 wherein said central controller is a tester workstation.