Staged Scenario Generation
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.
1 . An integrated circuit design verification generator comprising program elements residing on a non-transitory computer-readable storage-medium, the program elements enabling the computer to cause the generator to:
selectively generate a random verification scenario,
selectively receive a verification scenario that is injected from a higher stage level generator,
decode the verification scenario and generate a sequence of lower level scenarios using a callback mechanism, where for each verification scenario, a callback is added that can decode the verification scenario and generate the sequence of lower level scenarios, and
selectively inject the sequence of lower level scenarios into a lower stage level generator.