IP Library Granted Patent US 8,869,389
Granted Patent B2
US 8,869,389 · App. 13/677,547 · Granted Oct 28, 2014

Method of manufacturing an electronic device package

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Quick Facts
Patent No.
US 8,869,389
App. No.
13/677,547
Granted
Oct 28, 2014
Kind
B2
Abstract

An electronic device package 100 comprising a lead frame 105 having at least one lead 110 with a notch 205 . The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.

Claims (26)

1. A method of manufacturing an electronic device package, comprising:

providing a lead frame, said lead frame having a plurality of leads attached thereto;

forming a notch in at least one of said leads, wherein said notch includes at least one reentrant angle of greater than 180 degrees and said notch is located distal to a pre-defined separation region of said lead, wherein said notch goes all the way around lateral dimensions of said lead that are perpendicular to a long dimension of said lead; and

forming a metal plate that covers both a terminal portion said lead that is distal to said notch, and said notch.

2. The method of claim 1 , further including forming said notch in each of said plurality of leads.

3. The method of claim 2 , wherein said forming said notch includes forming a sized-sized opening in each of said leads such that said opening protrudes inward relative to an outer surface of said lead.

4. The method of claim 2 , wherein said forming said notch includes forming a same-sized step in each of said leads that protrudes outward relative to an outer surface of said lead.

5. The method of claim 1 , wherein said notch has at least two of said reentrant angles.

6. The method of claim 1 , wherein forming said metal plate includes placing said lead frame between first and second plating mask layers, wherein a proximal edge of said notch is adjacent to an outer edge of at least one of said plating mask layers and a distal edge of said notch is not covered by said plating mask layers.

7. The method of claim 6 , wherein forming said metal plate includes electro-depositing said metal plate on portions of said lead not covered by said first and second plating mask layers, wherein a first thickness of said metal plate located directly over said notch is greater than a second thickness of said metal plate located directly over a terminal portion of said lead that is distal to said notch.

8. The method of claim 7 , wherein electro-depositing said metal plate includes placing said lead frame and said plating mask layers in a metal plating solution and applying a voltage bias to said lead frame.

9. The method of claim 1 , further including attaching an electronic device to a device mounting portion of said lead frame, and bonding a wire from a landing pad of said electronic device to portions of said lead covered with said metal plate.

10. The method of claim 9 , further including covering said electronic device and said mounting portion of said lead frame with an insulating mold.

11. The method of claim 1 , further including severing said lead from a device mounting portion said lead frame by cutting within said pre-defined separation region to form a cut end of said lead, wherein said notch is located distal to said cut end.

12. A method of manufacturing an electronic device package, comprising:

providing a lead frame, said lead frame having a plurality of leads attached thereto;

in at least one of said leads, forming a region of reduced cross-section located distal to a pre-defined separation region of said lead, said region of reduced cross-section having at least one reentrant angle of greater than 180 degrees, said region of reduced cross-section circumscribing lateral dimensions of said lead that are perpendicular to a long dimension of said lead; and

forming a metal plate that covers both a terminal portion said lead that is distal to said region of reduced cross-section and said region of reduced cross-section.

13. The method of claim 12 , further including forming said region of reduced cross-section in each of said plurality of leads.

14. The method of claim 13 , wherein said forming said region of reduced cross-section includes forming a sized-sized opening in each of said leads such that said opening protrudes inward relative to an outer surface of said lead.

15. The method of claim 12 , wherein said region of reduced cross-section has at least two of said reentrant angles.

16. The method of claim 12 , wherein forming the metal plate includes forming a first thickness of said metal plate located directly over said region of reduced cross-section that is greater than a second thickness of said metal plate located directly over said terminal portion of said lead.

17. The method of claim 12 , wherein forming said metal plate includes electro-depositing said metal plate on said terminal portion of said lead and on said region of reduced cross-section.

18. The method of claim 12 , further including attaching an electronic device to a device mounting portion of said lead frame, and, bonding a wire from a landing pad of said electronic device to portions of said lead covered with said metal plate.

19. The method of claim 18 , further including covering said electronic device and said mounting portion of said lead frame with an insulating mold.

20. The method of claim 12 , further including severing said lead from a device mounting portion said lead frame by cutting within said pre-defined separation region to form a cut end of said lead, wherein said region of reduced cross-section is located distal to said cut end.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2012
From: GOLICK, LARRY W.; LOW, QWAI-HOONG; OSENBACH, JOHN W.; STAHLEY, MATTHEW E.
To: LSI CORPORATION
Reel/Frame 029302/0400 →