On-chip diode with fully depleted semiconductor devices
View Patent ↗An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions.
1. A method of forming an electrical device comprising:
forming a first conductivity type semiconductor device region including a first fin structure, a second conductivity type semiconductor device region including a second fin structure, and a diode region including a semiconductor island in a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate;
forming a first gate structure on the first fin structure in the first conductivity type semiconductor device region, and a second gate structure on the second fin structure in the second conductivity type semiconductor device region;
forming a first conductivity semiconductor material on the first fin structure on opposing sides of the first gate structure in the first conductivity type semiconductor device region and the semiconductor island in the diode region, wherein the first conductivity type semiconductor material on the first fin structure in the first conductivity type semiconductor device region provides a first conductivity source region and a first conductivity drain region; and
forming a second conductivity semiconductor material on the second fin structure on opposing sides of the second gate structure that is present in the second conductivity type semiconductor device region and on the first conductivity semiconductor material in the diode region, wherein the second conductivity type semiconductor material that is present on the second fin structure in the second conductivity type semiconductor device region provides a second conductivity source region and a second conductivity drain region, and a stack of the second conductivity semiconductor material and the first conductivity semiconductor material in the diode region provides a semiconductor diode.
2. The method of claim 1 , wherein prior to forming the second conductivity semiconductor material, an intrinsic semiconductor material is formed on the first conductivity type semiconductor material in the diode region, wherein the second conductivity semiconductor material that is formed on the diode region is in direct contact with the intrinsic semiconductor material.
3. The method of claim 2 , wherein after forming the first gate structure and the second gate structure the method further comprises:
depositing a dielectric layer on the SOI layer in the first conductivity type semiconductor device region, the second conductivity type semiconductor device region and the diode region; and
etching the dielectric layer to form a first gate sidewall spacer adjacent to the first gate structure in the first conductivity type semiconductor device region, a plurality of dielectric strips in the diode region, and a remaining portion of the dielectric layer on the second conductivity type semiconductor device region.
4. The method of claim 3 , wherein the forming the first conductivity semiconductor material on the SOI layer on opposing sides of the first gate structure in the first conductivity type semiconductor device region and the SOI layer in the diode region comprises an epitaxial deposition process, wherein the remaining portion of the dielectric layer obstructs the first conductivity semiconductor material from being formed on the second conductivity semiconductor device region and the plurality of strips obstructs the first conductivity semiconductor material from being formed on the portion of the SOI layer in the diode region that the plurality of strips are present on.
5. The method of claim 4 , wherein forming the intrinsic semiconductor material on the first conductivity type semiconductor material in the diode region comprises forming a first hard mask covering the first conductivity type semiconductor device region and the second conductivity type semiconductor device region;
removing the plurality of dielectric strips from the diode region; and
epitaxially forming the intrinsic semiconductor material on the first conductivity semiconductor material and the SOI layer in the diode region.
6. The method of claim 1 , wherein the forming the second conductivity semiconductor material on the SOI layer on opposing sides of the second gate structure that is present in the second conductivity type semiconductor device region and on the first conductivity semiconductor material in the diode region comprises forming a second hard mask over the first conductivity type semiconductor device region, and epitaxially forming the second conductivity semiconductor material.