METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE
Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.
1 . A method of programming an array of memory cells each comprising an antifuse in series with a diode, each antifuse comprising an insulator having a dielectric constant above 5, each diode comprising a thin film semiconductor material with a band gap smaller than that of silicon, the method comprising:
programming a selected one of the memory cells by applying a first voltage in a direction opposite that of natural current flow through the diode of the selected memory cell, the first voltage being sufficient to short the antifuse.
2 . The method of claim 1 , further comprising:
applying a second voltage to word lines contacting unselected ones of the memory cells; and
applying a third voltage to bit lines contacting the unselected ones of the memory cells, wherein the second and third voltages are substantially equal.
3 . The method of claim 2 , wherein the second and third voltages are approximately half the first voltage applied to the selected one of the memory cells.
4 . A method of programming a memory cell comprising an antifuse in series with a diode, the antifuse comprising an insulator having a dielectric constant above 5, the diode comprising a semiconductor material having a band gap smaller than that of silicon, the method comprising:
applying a first voltage in a direction of natural current flow through the diode, the first voltage being sufficient to short the antifuse; and
applying a second voltage in the direction of natural current flow through the diode, the second voltage being sufficient to cause current to pass through the shorted antifuse and to further reduce resistance of the shorted antifuse.
5 . The method of claim 4 , wherein the memory cell is a selected cell within an array of memory cells each contacting a bit line at its cathode end and a word line at its anode end, the method further comprising:
applying the first voltage to a word line contacting the selected memory cell;
applying a third voltage to word lines contacting unselected memory cells, wherein the third voltage is lower than the first voltage and above zero; and
applying a fourth voltage to bit lines contacting unselected memory cells, wherein the third voltage is lower than the first voltage and above zero.
6 . The method of claim 5 , wherein the third voltage is less than or equal to a threshold voltage of diodes in the memory cells.
7 . The method of claim 4 , wherein the second voltage is greater than the first voltage.
8 . The method of claim 4 , wherein the second voltage is less than the first voltage.
9 . A method of forming a memory cell, the method comprising:
forming a diode; and
forming a resistance-switching material layer coupled in series with the diode, wherein the resistance-switching material layer: (a) has a dielectric constant in the range of about 5 to about 27, and (b) comprises a material from the family consisting of X v O w , wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound.
10 . The method of claim 9 , wherein the diode comprises a band gap smaller than 1.12 electron volts.
11 . The method of claim 9 , wherein the diode comprises one or more of germanium (Ge) and a silicon germanium alloy (Si x Ge 1-x ).
12 . The method of claim 9 , wherein the resistance-switching material layer has a thickness between 20 and 65 angstroms.
13 . The method of claim 9 , wherein the resistance-switching material layer comprises HfO 2 or ZrO 2 .
14 . The method of claim 9 , wherein the memory cell is adapted to be programmed with a voltage less than about 5 volts.
15 . The method of claim 9 , wherein the diode comprises re-crystallized material.
16 . The method of claim 9 , wherein forming the diode comprises depositing semiconductor material.
17 . The method of claim 9 , wherein the diode is adapted to be read using a bias voltage less than about 2 volts.
18 . The method of claim 9 , further comprising forming an array of the memory cells.
19 . The method of claim 9 , further comprising forming a monolithic 3-dimensional array of the memory cells.