Solution for full speed, parallel DUT testing
View Patent ↗A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.
1. A system for use in automated test equipment, the system comprising:
a configurable integrated circuit (IC) including a plurality of testers, wherein each tester connects to a single data storage device under test to perform fully speed deterministic testing and includes
a functional acceleration block including,
pattern generation logic to generate write data based upon test patterns;
receiver logic to receive read data; and
hardware implemented comparison logic to compare the write data and corresponding read data; and
an interface protocol core, wherein each interface protocol core is directly connected to the pattern generation logic of a respective functional acceleration block using dedicated bus links, wherein one or more data storage devices under test are removably directly connected to respective ones of the plurality of interface cores, and wherein the interface cores wraps storage command into a standard protocol for transmission over a physical channel as electrical signals to send the write data to storage locations in the storage device under test and receive the corresponding read data from the storage locations in the storage device under test.
2. The system of claim 1 wherein the configurable IC is a field programmable gate array (FPGA).
3. The system of claim 1 wherein the configurable IC further includes one or more processors, wherein the one or more processors control operation of the pattern generation logic and the receiver logic.
4. The system of claim 1 wherein the configurable IC is substantially fully dedicated to automated testing.
5. The system of claim 1 wherein the configurable IC is optimized for high-speed parallel testing.
6. The system of claim 1 wherein the configurable IC generates a test stimulus including the write data to the attached data storage device under test at close to the maximum speed of the interface utilized to connect the data storage devices under test to the corresponding interface cores.
7. The system of claim 1 wherein the configurable IC comprises a plurality of testers, wherein each tester includes one of the functional acceleration blocks and a respective one of the interface cores, and wherein each tester tests different sets of data storage device under test.
8. The system of claim 1 wherein the configurable IC tests a plurality of the data storage devices in parallel.
9. The system of claim 1 wherein the configurable IC further includes one or more processors, wherein the one or more processors generate the test patterns.
10. The system of claim 1 wherein the functional acceleration blocks generate the test patterns.
11. The system of claim 1 wherein the functional acceleration blocks implement application specific functions as programmable circuits in the configurable IC, and wherein the application specific functions are executed with minimal or no oversight from a processor.
12. The system of claim 1 wherein the functional acceleration blocks implement application specific functions that enable faster functionality than software based functions running on a processor.
13. The system of claim 1 wherein the functional acceleration blocks implement application specific functions that enable lower implementation costs than a software based function running on a processor.
14. The system of claim 1 wherein the data storage devices under test are solid state drives.
15. An apparatus comprising:
a configurable integrated circuit (IC) for testing data storage device, wherein the configurable IC includes a plurality of testers implemented by an array of programmable logic blocks and a hierarch of reconfigurable interconnects, each tester including,
a functional acceleration block including,
pattern generation logic to generate write data based upon test patterns;
receiver logic to receive read data; and
comparison logic to compare the write data and corresponding read data; and
an interface protocol core that directly connects a single storage devices under test to the test pattern generation logic of the respective functional acceleration block of the tester using dedicated bus links, wherein the interface cores send the write data to storage locations in the data storage device under test and receive the corresponding read data from the storage location in the data storage device under test, and
wherein each functional acceleration block and corresponding interface core are in close proximity to a respective data storage device under test to allow optimized connectivity with regards to minimal management overhead, matched bandwidth and latency to avoid bottlenecks and to allow communication with the data storage device under test at maximum speed.
16. The apparatus of claim 15 wherein the configurable IC is a field programmable gate array (FPGA).
17. The apparatus of claim 15 wherein the configurable IC is substantially fully dedicated to automated testing.
18. The apparatus of claim 15 wherein the configurable IC is optimized for highspeed parallel testing a plurality of the data storage device under test.
19. The apparatus of claim 15 wherein the configurable IC generates a test stimulus including the write data to the attached data storage device under test at close to the maximum speed of the interface utilized to connect the data storage devices under test to the corresponding interface cores.