IP Library Granted Patent US 8,685,830
Granted Patent B2
US 8,685,830 · App. 13/705,437 · Granted Apr 1, 2014

Method of filling shallow trenches

Inventors: Fan Chen (Shanghai, CN); Xiongbin Chen (Shanghai, CN); Kai Xue (Shanghai, CN); Keran Zhou (Shanghai, CN); Jia Pan (Shanghai, CN); Hao Li (Shanghai, CN); Yongcheng Wang (Shanghai, CN)
Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
H01L21/76H01L21/76224H01L21/76283
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Quick Facts
Patent No.
US 8,685,830
App. No.
13/705,437
Granted
Apr 1, 2014
Kind
B2
Abstract

A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.

Claims (20)

1. A method of filling shallow trenches, the method comprising the steps of:

providing a silicon substrate, the silicon substrate having a mask layer formed thereon;

etching the silicon substrate to form one or more shallow trenches therein;

depositing a first oxide layer, which serves as a first pad oxide layer, over surface of the silicon substrate;

depositing a second oxide layer over surface of the silicon substrate;

etching the second oxide layer by using a dry etch-back process to form inner sidewalls in the one or more trenches, wherein the dry etch-back process has a high etching selectivity ratio of the second oxide layer to the first oxide layer, such that the first oxide layer is remained after the dry etch-back process;

removing the inner sidewalls by using a wet etching process, wherein the first pad oxide layer is simultaneously removed by the wet etching process so that the underlying silicon is exposed in each of the one or more trenches;

growing a silicon dioxide layer, which serves as a second pad oxide layer, over a surface of each of the one or more trenches by thermal oxidation of the exposed underlying silicon; and

filling the one or more trenches with an isolation dielectric material.

2. The method according to claim 1 , wherein a shallow trench isolation process is adopted to etch the silicon substrate to form the one or more shallow trenches.

3. The method according to claim 1 , wherein the first oxide layer is a non-doped silicon dioxide layer, and the second oxide layer is a heavily N-doped silicon dioxide layer.

4. The method according to claim 3 , wherein the non-doped silicon dioxide layer has a thickness of 100 Å to 300 Å and is formed by sub-atmospheric chemical vapor deposition at a temperature of 300° C. to 500° C.

5. The method according to claim 3 , wherein the heavily N-doped silicon dioxide layer has a thickness of 300 Å to 1000 Å and a doping concentration of 4% to 8% by weight.

6. The method according to claim 1 , wherein the thermal oxidation is conducted at a temperature of 800° C. to 1150° C., and the second pad oxide layer formed by the thermal oxidation has a thickness of 100 Å to 200 Å.

7. The method according to claim 1 , wherein the isolation dielectric material is silicon dioxide, and is filled by a high-density plasma chemical vapor deposition process.

8. The method according to claim 1 , further comprising a step of forming a metal silicide after the step of filling the one or more trenches with an isolation dielectric material.

9. The method according to claim 8 , wherein the step of forming a metal silicide includes:

removing the mask layer by wet etching so as to expose the underlying silicon;

depositing a refractory metal in regions where the underlying silicon is exposed; and

performing a high-temperature annealing process to form the metal silicide.

Assignments (2)
MERGER Recorded May 13, 2014
From: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
To: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 032885/0047 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2012
From: CHEN, FAN; CHEN, XIONGBIN; XUE, KAI; ZHOU, KERAN; PAN, JIA; LI, HAO; WANG, YONGCHENG
To: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
Reel/Frame 029408/0818 →
Priority Claims (1)
CN 2011 1 0398277 · Dec 5, 2011 · national
Continuity (1)
Related Publication 20130143386A1 · Jun 6, 2013