Coalesced nanowire structures with interstitial voids and method for manufacturing the same
View Patent ↗A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.
1. A semiconductor device, comprising:
a plurality of first conductivity type semiconductor nanowire cores located over a support;
a continuous second conductivity type semiconductor layer extending over and around the cores;
a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores; and
a first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids;
an active region shell around each nanowire core, wherein the active region shell comprises at least one quantum well and the second conductivity type semiconductor layer surrounds the at least one quantum well to form a light emitting p-i-n junction at each nanowire core surrounded by the at least one quantum well shell; and
wherein a portion of a space between adjacent active region shells is completely filled with the continuous second conductivity type semiconductor layer.
2. The device of claim 1 , wherein the device comprises a light emitting diode (LED) device.
3. The device claim 2 , wherein the support comprises a semiconductor substrate.
4. The device claim 2 , wherein the first electrode layer is transparent.
5. The device of claim 2 , wherein the cores comprise semiconductor nanowires epitaxially extending from portions of a semiconductor surface of the support exposed through openings in an insulating mask layer located on the support.
6. The device of claim 1 , wherein the first conductivity type comprises n-type, the second conductivity type comprises p-type and the first electrode layer comprises a p-electrode layer.
7. The device of claim 6 , wherein the support comprises an n-type semiconductor buffer layer on a substrate.
8. The device of claim 7 , wherein the substrate comprises an n-Si substrate, the buffer layer comprises an n-GaN or n-A 1 GaN layer, the cores comprise n-GaN nanowires epitaxially extending from portions of the buffer layer surface exposed through openings in an insulating mask layer on the buffer layer, the at least one quantum well comprises an InGaN quantum well, and the second conductivity type semiconductor layer comprises a p-GaN layer.
9. The device of claim 1 , further comprising a second electrode layer which electrically connects to the first conductivity type nanowire cores.
10. The device of claim 1 , wherein the cores have a hexagonal cross sectional shape and vertices of each of the hexagonal cross sectional shape points to less than two vertices of adjacent cores to form triangular interstitial voids in the second conductivity type semiconductor layer.
11. The device of claim 1 , wherein the cores have a substantially square cross sectional shape and each vertex of the square cross sectional shape points to less than three vertices of adjacent cores to form square or rectangular interstitial voids in the second conductivity type semiconductor layer.
12. The device of claim 1 , wherein the second conductivity type semiconductor layer is substantially planar.
13. A method of making a semiconductor device, comprising:
epitaxially growing plurality of first conductivity type semiconductor nanowire cores from portions of a semiconductor surface of a support exposed through openings in an insulating mask layer on the support;
forming semiconductor active region shells on the cores;
growing the continuous second conductivity type semiconductor layer extending over and around the cores and the shells, such that a plurality of interstitial voids are formed in the second conductivity type semiconductor layer extending between the cores during the step of growing; and
forming a first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids, wherein the active region shells comprise at least one quantum well and the continuous second conductivity type semiconductor layer surrounds the at least one quantum well to form a light emitting p-i-n junction at each nanowire core surrounded by the at least one quantum well shell; and
wherein a portion of a space between adjacent active region shells is completely filled with the continuous second conductivity type semiconductor layer.
14. The method of claim 13 , wherein the device comprises a light emitting diode (LED) device, the first conductivity type comprises n-type, the second conductivity type comprises p-type and the first electrode layer comprises a p-electrode layer.
15. The method of claim 14 , further comprising a second electrode layer which electrically connects to the n-type nanowire cores.
16. The method of claim 14 , wherein the support comprises an n-type semiconductor buffer layer on a substrate, the substrate comprises an n-Si substrate, the buffer layer comprises an n-GaN or n-A 1 GaN layer, the cores comprise n-GaN nanowires, the at least one quantum well comprises an InGaN quantum well, and the second conductivity type semiconductor layer comprises a p-GaN layer.
17. The method of claim 14 , wherein the cores are positioned such that a non-tessellated configuration is provided when the second conductivity type semiconductor layer is grown to form the interstitial voids during growth.