Integrated circuit devices and systems having programmable impedance elements with different response types
View Patent ↗An integrated circuit (IC) device can include a memory array having memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom. A memory device can also have a plurality of access ports, each configurable to access any of the different portions of the memory array. A memory device can further include a read circuit configured to read data values from the different portions according to the response type of each portion.
1. An integrated circuit (IC) device, comprising:
a memory array including memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and
a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom according to the different response types.
2. The IC device of claim 1 , wherein:
the IC device is a system-on-chip (Soc) device; and
the logic section includes at least one processor circuit.
3. The IC device of claim 2 , wherein:
the memory array includes
a first portion configured to store data with a first data retention time, and
a second portion configured to store data with a second data retention time shorter than the first data retention time; and
the at least one processor circuit is configured to access process instruction data from the first portion.
4. The IC device of claim 2 , further including:
an address translator configured to translate an address space accessed by the processor into physical addresses of the memory array.
5. The IC device of claim 4 , wherein:
the address translator is configured to translate a first range of processor addresses into locations within the memory array having a first data retention time, and to translate a second range of processor addresses into locations within the memory array having a second data retention time.
6. The IC device of claim 4 , wherein:
the first and second ranges of processor addresses are programmable.
7. The IC device of claim 2 , further including:
a configuration register; and
the at least one processor is configured to access different portions of the memory array in response to values stored in the configuration register.
8. The IC device of claim 1 , further including:
a configuration register; and
the memory array is dividable into portions with different data retention times in response to values stored in the configuration register.
9. The IC device of claim 1 , wherein:
the different response types are selected from the group of: different read speeds, different write speeds, different power consumption during accesses, different data retention times, and different data endurance.
10. The IC device of claim 1 , wherein:
the IC device comprises a plurality of blocks, the blocks including the memory array and the logic section, each block being disabled in response to states of configuration programmable impedance elements, each formed with a solid ion conductor.
11. An integrated circuit (IC) device, comprising:
a memory array including memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and
a plurality of access ports, each configurable to access any of the different portions of the memory array.
12. The IC device of claim 11 , further including:
each portion includes an address decoder configured to access a group of memory elements of the portion in response to a received address value; and
each port includes an address bus; and
an address selection circuit corresponding to each portion, each address selection circuit configured to apply an address from one of the addresses buses to the address decoder of the portion.
13. The IC device of claim 11 , further including:
each port includes a data bus;
each portion includes an input/output (I/O) circuit configured to access storage locations within the portion; and
a data selection circuit corresponding to each portion, each data selection circuit configured transfer data between the I/O circuit and one of the data buses.
14. The IC device of claim 11 , wherein:
at least a first portion of the memory array is configured to store data in a nonvolatile fashion; and
at least a second portion is configured to store data with a shorter data retention time than the first portion.
15. The IC device of claim 11 , wherein:
each access ports is configurable to access one of the memory portions according to configuration information.
16. The IC device of claim 11 , wherein:
the different response types are selected from the group of: different read speeds, different write speeds, different power consumption during accesses, different data retention times, and different data endurance.
17. An integrated circuit (IC) device, comprising:
a memory array including memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and
a read circuit configured to read data values from the different portions according to the response type of each portion.
18. The IC device of claim 17 , wherein:
the read circuit comprises different read circuit sections, each configured to read according to a different response type.
19. The IC device of claim 17 , wherein:
the read circuit comprises at least one read circuit section configurable to read data according to any of a plurality of different response types.
20. The IC device of claim 17 , wherein:
the read circuit is configured to read single data values from single memory elements in first portions of the memory array, and to read single data values from multiple memory elements in second portions of the memory array.
21. The IC device of claim 17 , wherein:
the different response types are selected from the group of: different read speeds, different write speeds, different power consumption during accesses, different data retention times, and different data endurance.
22. The IC device of claim 17 , wherein:
the memory array comprises a plurality of memory cells, each memory cell including a memory element coupled to a bit line; and
a read circuit is programmable between at least a first mode and second mode of operation, the read circuit sensing a data value based on a single bit line in the first mode, and a pair of bit lines in the second mode.
23. The IC device of claim 17 , wherein:
the read circuit comprises capacitance sensing circuits.