IP Library Granted Patent US 8,829,489
Granted Patent B2
US 8,829,489 · App. 13/714,300 · Granted Sep 9, 2014

Nitride semiconductor template and light-emitting diode

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Quick Facts
Patent No.
US 8,829,489
App. No.
13/714,300
Granted
Sep 9, 2014
Kind
B2
Abstract

A nitride semiconductor template includes a substrate, and a group III nitride semiconductor layer formed on the substrate and including a Si-doped layer doped with Si as an uppermost layer thereof. The group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm. The Si-doped layer includes a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×10 17 cm −3 and not more than 5×10 17 cm −3 at the outermost surface of the group III nitride semiconductor layer.

Claims (25)

1. A nitride semiconductor template, comprising:

a substrate; and

a group III nitride semiconductor layer formed on the substrate and comprising a Si-doped layer doped with Si as an uppermost layer thereof,

wherein the group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm, and

wherein the Si-doped layer comprises a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×10 17 cm −3 and not more than 5×10 17 cm −3 at the outermost surface of the group III nitride semiconductor layer.

2. The nitride semiconductor template according to claim 1 , wherein the group III nitride semiconductor layer comprises an O-doped layer doped with O (oxygen) between the substrate and the Si-doped layer.

3. The nitride semiconductor template according to claim 2 , wherein the O-doped layer has an O-impurity concentration of not less than 1×10 16 cm −3 and not more than 3×10 19 cm −3 and an average carrier concentration in a thickness direction of not less than 8×10 17 cm −3 and not more than 1×10 18 cm −3 .

4. The nitride semiconductor template according to claim 1 , wherein the Si-doped layer comprises a high Si concentration layer having a uniform carrier concentration in a thickness direction, and

wherein the Si concentration gradient layer has a carrier concentration that gradually decreases from the high Si concentration layer toward the outermost surface.

5. The nitride semiconductor template according to claim 4 , wherein the carrier concentration of the high Si concentration layer is not less than 1×10 17 cm −3 and not more than 1×10 19 cm −3 .

6. The nitride semiconductor template according to claim 1 , wherein the substrate comprises a PSS (Patterned Sapphire Substrate) comprising a plurality of convex portions on a surface thereof.

7. The nitride semiconductor template according to claim 1 , wherein the template has a surface resistivity of not less than 10 Ω/sq and not more than 30 Ω/sq.

8. The nitride semiconductor template according to claim 1 , wherein the template has a half-value width at a (0004) plane of not more than 100 seconds by X-ray diffraction measurement.

9. A light-emitting diode, comprising:

a sapphire substrate;

an AlN buffer layer formed on the sapphire substrate;

an n-type group III nitride semiconductor layer formed on the AlN buffer layer;

a multiple quantum well layer formed on the n-type group III nitride semiconductor layer;

a p-type nitride semiconductor layer formed on the multiple quantum well layer;

an exposed portion of the n-type group III nitride semiconductor layer formed by etching from the p-type nitride semiconductor layer to the n-type group III nitride semiconductor layer;

an n-type electrode formed on the exposed portion of the n-type group III nitride semiconductor layer; and

a p-type electrode formed on the p-type nitride semiconductor layer,

wherein the n-type group III nitride semiconductor layer comprises a group III nitride semiconductor layer comprising a Si-doped layer doped with Si as an uppermost layer thereof,

wherein the group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm, and

wherein the Si-doped layer comprises a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×10 17 cm −3 and not more than 5×10 17 cm −3 at the outermost surface of the group III nitride semiconductor layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2016
From: SCIOCS COMPANY LIMITED
To: SUMITOMO CHEMICAL COMPANY, LIMITED
Reel/Frame 037827/0453 →
COMPANY SPLIT Recorded Jul 24, 2015
From: HITACHI METALS, LTD.
To: SCIOCS COMPANY LIMITED
Reel/Frame 036181/0104 →
MERGER Recorded Feb 15, 2014
From: HITACHI CABLE, LTD.
To: HITACHI METALS, LTD.
Reel/Frame 032268/0297 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2012
From: KONNO, TAICHIROO; FUJIKURA, HAJIME
To: HITACHI CABLE, LTD.
Reel/Frame 029675/0139 →