Via connection structures, semiconductor devices having the same, and methods of fabricating the structures and devices
A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.
1. A semiconductor device, comprising:
a silicon substrate;
an insulating layer on a first side of the silicon substrate;
an interconnection structure in the insulating layer;
a via structure vertically penetrating the silicon substrate, the via structure protruding into the insulating layer and the interconnection structure;
an internal circuit structure on a second side of the silicon substrate, the second side being opposite the first side, the internal circuit structure including:
unit devices, and
internal connection structures, at least one of the internal connection structures electrically connecting the via structure to a second side pad, and at least one internal connection structure electrically connecting the via structure to at least one of the unit devices; and
the second side pad on the internal circuit structure.
2. The semiconductor device of claim 1 , further comprising
an insulating material between the silicon substrate and the insulating layer.
3. The semiconductor device of claim 1 , wherein
a portion of the via structure includes a via core, a via barrier layer on the via core, and a via liner on the via barrier layer.
4. The semiconductor device of claim 1 , wherein
the interconnection structure includes an interconnection barrier layer lining a groove in the insulating layer and covering a portion of the via structure;
the interconnection structure includes an interconnection filling a remainder of the groove.
5. The semiconductor device of claim 4 , wherein the via structure protrudes into the interconnection.
6. The semiconductor device of claim 1 , wherein a portion of the via structure in the interconnection structure forms an end of the via structure, and the end is rounded.
7. The semiconductor device of claim 1 , wherein a portion of the via structure in the interconnection structure forms an end of the via structure, and the end is planar.
8. The semiconductor device of claim 1 , wherein:
the interconnection structure includes a via region, a pad region and an interconnection region, the interconnection region electrically connects the via region and the pad region;
a pad is on the pad region; and
the via structure protrudes into the via region.
9. The semiconductor device of claim 8 , wherein:
the via region and the pad region have greater horizontal widths than a horizontal width of the interconnection region, and the via region has at least one portion with a greater horizontal width than the horizontal width of the pad region.
10. The semiconductor device of claim 1 , further comprising:
a first side pad on the interconnection structure; and
an alignment key structure in the insulating layer.
11. The semiconductor device of claim 1 , wherein:
the internal circuit structure includes,
a first interlayer insulating layer on the second side of the silicon substrate, the first interlayer insulating layer covering at least one of the unit devices, and
a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer covering at least one of the internal connection structures; and
the via structure is in at least a portion of the first interlayer insulating layer and not the second interlayer insulating layer.
12. The semiconductor device of claim 1 , wherein:
the internal circuit structure includes,
a first interlayer insulating layer on the second side of the silicon substrate, the first interlayer insulating layer covering at least one of the unit devices, and
a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer covering at least one of the internal connection structures; and
the via structure is not in the first interlayer insulating layer and is not in the second interlayer insulating layer.
13. The semiconductor device of claim 1 , wherein the insulating layer is a single layer.
14. The semiconductor device of claim 1 , wherein:
the insulating layer includes a first insulating layer on the silicon substrate, and a second insulating layer on the first insulating layer;
the interconnection structure is only in the second insulating layer.
15. The semiconductor device of claim 14 , wherein the first insulating layer is disposed between the via structure and the second insulating layer.
16. The semiconductor device of claim 14 , wherein:
the interconnection structure includes an interconnection barrier layer lining a groove in the insulating layer and covering a portion of the via structure;
the interconnection structure includes an interconnection filling a remainder of the groove.
17. The semiconductor device of claim 16 , wherein the via structure protrudes into the interconnection.
18. The semiconductor device of claim 14 , wherein:
the interconnection structure includes a via region, a pad region and an interconnection region, the interconnection region electrically connects the via region and the pad region;
a pad is on the pad region; and
the via structure protrudes into the via region.
19. The semiconductor device of claim 18 , wherein:
the via region and the pad region have greater horizontal widths than a horizontal width of the interconnection region, and the via region has at least one portion with a greater horizontal width than the horizontal width of the pad region.
20. A semiconductor device, comprising:
a silicon substrate;
a MOS transistor on a front-side of the silicon substrate;
interlayer insulating layers covering the MOS transistor on the front-side of the silicon substrate;
a front-side passivation layer on the interlayer insulating layers;
a front-side I/O pad on the front-side passivation layer;
a back-side insulating layer on a back-side of the silicon substrate;
a back-side interconnection structure in the back-side insulating layer; and
a via structure vertically penetrating the silicon substrate and the back-side insulating layer,
wherein a back-side end of the via structure protrudes into the back-side interconnection structure.
21. The semiconductor device of claim 20 , wherein the interlayer insulating layer includes:
a first interlayer insulating layer covering the MOS transistor; and
a second interlayer insulating layer on the first insulating layer,
wherein the via structure penetrates the first interlayer insulating layer and does not penetrates the second interlayer insulating layer, and
wherein a front-side end of the via structure and the first interlayer insulating layer are co-planar.
22. The semiconductor device of claim 21 , further comprising:
a via pad on the front-side end of the via structure and the first interlayer insulating layer; and
a back-side I/O pad on the back-side interconnection.
23. The semiconductor device of claim 21 , further comprising:
an inner via and an inner interconnection in the second interlayer insulating layer,
wherein the inner via and the inner interconnection electrically connect the via structure to the front-side I/O pad.
24. A semiconductor device comprising:
a substrate having a first side and a second side opposite the first side;
a first insulating layer on the first side of the silicon substrate;
a first interconnection structure in the first insulating layer;
a first passivation layer on the first insulating layer;
a first pad on the first passivation layer, the first pad being electrically connected to the first interconnection structure;
a second insulating layer on the second side of the silicon substrate;
a second interconnection structure in the second insulating layer;
a second passivation layer on the second insulating layer and the second interconnection structure;
a second pad on the second passivation layer, the second pad being electrically connected to the second interconnected structure; and
a via structure vertically penetrating from the first side of the substrate to the second side of the substrate,
wherein the via structure has a first end nearing the first side of the substrate, and a second end nearing the second side of the substrate and protruding into the second interconnection structure.
25. The semiconductor device of claim 24 , further comprising:
a via pad on the first end of the via structure, the via pad being electrically connected to the first pad,
wherein the second interconnection structure comprises:
an interconnection barrier layer; and
an interconnection,
wherein the interconnection barrier layer conformably covers an end protruding into the second interconnection structure.