Method and system adapted for converting software constructs into resources for implementation by a dynamically reconfigurable processor
View Patent ↗A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.
1. In an information technology system, a method comprising:
a. accessing a first data flow model of a first a software coded or software coded logical statement or instruction (“first software construct type”), wherein the first data flow model includes at least one resource, the at least one resource modeling a component of a dynamically reconfigurable processor, wherein the dynamically reconfigurable processor comprises:
i. an instruction bus;
ii. an instruction pipe coupled with the instruction bus;
iii. a reconfigurable logic circuit array coupled with the instruction pipe;
iv. a data pipe coupled with the reconfigurable logic circuit array; and
v. a data bus coupled with the reconfigurable logic circuit array;
b. initiating a compilation of a plurality of software constructs;
c. determining a first instance of a software construct of the plurality of software constructs that conforms to the first software construct type; and
d. expressing the first instance of the first software construct type as an instance of the first data flow model in a resultant data flow model generated from the compilation of the plurality of software constructs.
2. The method of claim 1 , wherein the first data flow model comprises a plurality of resources, wherein each resource represents at least one component of a dynamically reconfigurable processor.
3. The method of claim 1 , wherein the first data flow model comprises a function call.
4. The method of claim 1 , wherein the resultant data flow model is comprised within a bubble.
5. The method of claim 4 , further comprising:
e. determining that the data flow model includes a loop logic;
f. splitting the bubble into a first bubble and a second bubble, wherein:
i. the first bubble includes logic precedent to the loop logic;
ii. the second bubble includes the loop logic;
g. adding a first processor reconfiguration command to the first bubble to direct the dynamically reconfigurable processor to reconfigure; and
h. adding a second processor reconfiguration command to the second bubble to direct the dynamically reconfigurable processor to reconfigure.
6. The method of claim 4 , further comprising:
e. determining that the bubble includes a function call;
f. splitting the bubble into a first bubble and a second bubble, wherein:
i. the first bubble includes logic precedent to the function call;
ii. the second bubble includes the function call;
g. adding a first processor reconfiguration command to the first bubble to direct the dynamically reconfigurable processor to reconfigure; and
h. adding a second processor reconfiguration command to the second bubble to direct the dynamically reconfigurable processor to reconfigure.
7. The method of claim 4 , further comprising:
e. determining that the bubble exhibits a potential memory operation overlap condition; and
f. adding a processor reconfiguration command to the bubble to direct the dynamically reconfigurable processor to reconfigure.
8. The method of claim 4 , further comprising:
e. determining that the bubble includes a condition logic;
f. splitting the bubble into a first bubble and a second bubble, wherein:
i. the first bubble includes logic precedent to the condition logic;
ii. the second bubble includes the condition logic; and
g. adding a processor reconfiguration command to the second bubble to direct the dynamically reconfigurable processor to reconfigure.
9. The method of claim 4 , further comprising;
e. forming a listing of resource constraints of the dynamically reconfigurable processor;
f. determining that the bubble of data includes a plurality of resources that exceeds the resource constraints of the dynamically reconfigurable processor; and
g. splitting the bubble into a first bubble and a second bubble, wherein at least the first bubble does not exceed the resource constraints of the dynamically reconfigurable processor.
10. The method of claim 9 , further comprising;
e. determining that the second bubble includes a plurality of resources that exceeds the resource constraints of the dynamically reconfigurable processor; and
f. splitting the second bubble into a third bubble and a fourth bubble, wherein at least the third bubble does not exceed the resource constraints of the dynamically reconfigurable processor.
11. In an information technology system, a method comprising:
a. forming a library of software coded or software coded logical statements or instructions (“software construct types”);
b. generating a library of data flow models, wherein at least one data flow model uniquely corresponds to a specific software construct type, and the at least one data flow model comprises at least one resource representing a component of a dynamically reconfigurable processor, wherein the dynamically reconfigurable processor comprises:
i. an instruction bus;
ii. an instruction pipe coupled with the instruction bus;
iii. a reconfigurable logic circuit array coupled with the instruction pipe;
iv. a data pipe coupled with the reconfigurable logic circuit array; and
v. a data bus coupled with the reconfigurable logic circuit array;
c. accessing a plurality of software constructs;
d. compiling the plurality of software constructs wherein a resultant data flow model is generated; and
e. representing at least one software construct at least partially by the at least one data flow model.
12. The method of claim 11 , wherein a plurality of the data flow models of the library of data flow models each comprise at least one resource representing a component of a dynamically reconfigurable processor.
13. The method of claim 11 , wherein the at least one data flow model of the library of data flow models comprises a function call.
14. The method of claim 11 , wherein the resultant data flow model comprises at least part of an instruction of a dynamically reconfigurable processor.
15. The method of claim 11 , wherein the resultant data flow model comprises a plurality of instances of the at least one data flow model of the library of data flow models.
16. The method of claim 11 , wherein the resultant data flow model comprises a loop logic.
17. The method of claim 11 , wherein the resultant data flow model comprises a condition logic.
18. The method of claim 11 , wherein the resultant data flow model comprises a function call.
19. The method of claim 11 , wherein the resultant data flow model comprises a loop logic.
20. An information technology system comprising:
a. a library of software coded or software coded logical statements or instructions (“software construct types”);
b. a library of data flow models, wherein at least one data flow model uniquely corresponds to a unique software construct type, and the at least one data flow model comprising at least one resource representing a component of a dynamically reconfigurable processor, wherein the dynamically reconfigurable processor comprises:
i. an instruction bus;
ii. an instruction pipe coupled with the instruction bus;
iii. a reconfigurable logic circuit array coupled with the instruction pipe;
iv. a data pipe coupled with the reconfigurable logic circuit array; and
v. a data bus coupled with the reconfigurable logic circuit array;
c. a plurality of software constructs; and
d. a software compiler, the compiler adapted to compile the plurality of software constructs whereby a resultant data flow model is generated and at least one software construct is at least partially represented by the at least one data flow model.