Thin integrated circuit chip-on-board assembly and method of making
View Patent ↗An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.
1. A method of forming an integrated circuit assembly, the method comprising:
providing a semiconductor-on-insulator including:
an insulating layer having a first surface and a second surface;
an active layer contacting the first surface of the insulating layer; and
a substrate layer contacting the second surface of the insulating layer;
providing a handle body having a surface;
coupling the active layer to the surface of the handle body;
removing the substrate layer;
forming a first metal bond pad on the second surface of the insulating layer;
wherein the first metal bond pad is electrically connected to the active layer;
forming a solder bump on the first metal bond pad;
providing a printed circuit board having a second metal bond pad;
connecting the solder bump to the second metal bond pad; and
removing the handle body.
2. The method of claim 1 , further comprising:
after the step of forming a solder bump on the first metal bond pad, singulating the active layer and the handle body.
3. The method of claim 1 , further comprising:
before the step of coupling the active layer to the surface of the handle body, forming a first passivation layer on the active layer.
4. The method of claim 1 , further comprising:
before the step of forming a first metal bond pad on the second surface of the insulating layer, forming a second passivation layer on the second surface of the insulating layer.
5. The method of claim 1 , further comprising:
before the step of coupling the active layer to the surface of the handle body, forming a thermal spreading layer above the insulating layer.
6. The method of claim 5 , wherein the thermal spreading layer comprises a metal.
7. The method of claim 5 , wherein the thermal spreading layer comprises one of copper, aluminum, gold, silver, or tungsten.
8. The method of claim 1 , wherein the substrate of the semiconductor-on-insulator comprises a silicon wafer.
9. The method of claim 1 , wherein the step of removing the substrate comprises mechanical grinding.
10. The method of claim 1 , wherein the active layer comprises a complementary metal-oxide-semiconductor circuit.
11. The method of claim 1 , wherein the active layer includes passive devices.
12. The method of claim 1 , wherein the step of coupling the surface of the handle body to the active layer comprises:
applying an adhesive layer to the surface of the handle body; and
contacting the active layer to the adhesive layer.
13. The method of claim 1 , wherein the step of removing the handle body comprises one of the following: use of mechanical force, a chemical treatment, ultraviolet irradiation, or laser irradiation.
14. The method of claim 1 , wherein the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly.