IP Library Granted Patent US 8,912,646
Granted Patent B2
US 8,912,646 · App. 13/725,306 · Granted Dec 16, 2014

Integrated circuit assembly and method of making

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Quick Facts
Patent No.
US 8,912,646
App. No.
13/725,306
Granted
Dec 16, 2014
Kind
B2
Abstract

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.

Claims (19)

1. An integrated circuit assembly comprising:

an insulating layer having a first surface and a second surface;

a first active layer contacting the first surface of the insulating layer;

a metal bond pad formed on the second surface of the insulating layer;

wherein the metal bond pad is electrically connected to the first active layer;

a substrate having a first surface and a second surface, the first active layer being coupled to the second surface of the substrate;

a second active layer formed on the first surface of the substrate;

a first wafer including the insulating layer and the first active layer; and

a second wafer bonded to the first wafer, the second wafer including the substrate and the second active layer.

2. The integrated circuit assembly of claim 1 , further comprising:

a printed circuit board, the printed circuit board being electrically connected to the metal bond pad.

3. The assembly of claim 1 , wherein the substrate is less than 100 microns thick.

4. The assembly of claim 1 , wherein the substrate is less than 50 microns thick.

5. The assembly of claim 1 , wherein the substrate is less than 30 microns thick.

6. The assembly of claim 1 , wherein the first active layer or the second active layer includes passive devices.

7. The assembly of claim 2 , wherein the printed circuit board is electrically connected with a solder bump to the first active layer.

8. The assembly of claim 2 , wherein the printed circuit board is electrically connected to the second active layer through a wire bond.

9. The assembly of claim 2 , wherein the printed circuit board is electrically connected with a solder bump to the second active layer.

10. The assembly of claim 2 , wherein the printed circuit board is electrically connected to the first layer through a wire bond.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: QUALCOMM SWITCH CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 038794/0663 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS PATENT NUMBER 9029901 TO THE CORRECT PATENT NO. 9029201 AS PREVIOUSLY RECORDED ON REEL 036812 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST AGAINST ALL PATENTS SET FORTH HEREIN. Recorded Oct 20, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036907/0785 →
CHANGE OF NAME Recorded Oct 16, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: QUALCOMM SWITCH CORP.
Reel/Frame 036877/0140 →
TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST (PATENTS) Recorded Oct 7, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036812/0429 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME IN THE ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED AT REEL: 029522 FRAME: 0121. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 20, 2015
From: STUBER, MICHAEL A.; MOLIN, STUART B.; DRUCKER, MARK; FOWLER, PETER
To: IO SEMICONDUCTOR INCORPORATED
Reel/Frame 036138/0930 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033134 FRAME: 0338. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 15, 2015
From: IO SEMICONDUCTOR INCORPORATED
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 036109/0237 →
CHANGE OF NAME Recorded Jun 11, 2014
From: IO SEMICONDUCTOR, INC.
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 033134/0338 →
SECURITY AGREEMENT Recorded Feb 4, 2013
From: IO SEMICONDUCTOR INCORPORATED
To: HSBC BANK AUSTRALIA LIMITED
Reel/Frame 029751/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2012
From: STUBER, MICHAEL A.; MOLIN, STUART B.; DRUCKER, MARK; FOWLER, PETER
To: IO SEMICONDUCTOR, INC.
Reel/Frame 029522/0121 →