Integration of Ru wet etch and CMP for beol interconnects with Ru layer
View Patent ↗Embodiments described herein provide approaches for interconnect formation in a semiconductor device. Specifically, a Cu layer is removed to a top surface of an Ru layer using CMP, the Cu layer is removed to form a recess within each of a plurality of trenches of a dielectric of the semiconductor device, and the Ru layer is removed using an etch process (e.g., a wet etch). An additional CMP is performed to reach the desired target trench height and to planarize the wafer.
1. A method for forming a device, the method comprising:
providing a semiconductor structure comprising:
a dielectric layer formed over a substrate, the dielectric layer having a plurality of trenches formed therein;
a first liner layer formed over the dielectric layer;
a ruthenium (Ru) layer formed over the first liner layer; and
a copper (Cu) layer formed over the Ru layer, wherein at least a portion of the dielectric layer, at least a portion of the first liner layer, and at least a portion of the Ru layer are disposed between each portion of the Cu layer and the substrate;
removing the Cu layer to a top surface of the Ru layer;
removing the Cu layer to form a recess within each of the plurality of trenches;
etching the Ru layer over the first liner layer and within the recess of each of the plurality of trenches; and
planarizing the semiconductor structure.
2. The method according to claim 1 , the providing the IC structure further comprising a second liner layer formed over the first liner layer.
3. The method according to claim 2 , the second liner layer comprising tantalum.
4. The method according to claim 1 , the first liner layer comprising tantalum nitride.
5. The method according to claim 1 , the etching the Ru layer comprising performing a wet etch.
6. The method according to claim 1 , the planarizing the semiconductor structure comprising performing a chemical mechanical planarization (CMP) of the dielectric layer, the first liner layer, and the Ru layer.
7. The method according to claim 1 , the planarizing the IC structure comprising performing a CMP of the dielectric layer, the first liner layer, the second liner layer, and the Ru layer.
8. A method for interconnect formation, the method comprising:
providing an integrated circuit (IC) structure comprising:
a dielectric layer formed over a substrate, the dielectric layer having a plurality of trenches formed therein;
a first liner layer formed over the dielectric layer;
a ruthenium (Ru) layer formed over the first liner layer; and
a copper (Cu) layer formed over the Ru layer, wherein at least a portion of the dielectric layer, at least a portion of the first liner layer, and at least a portion of the Ru layer are disposed between each portion of the Cu layer and the substrate;
removing the Cu layer to a top surface of the Ru layer;
removing the Cu layer to form a recess within each of the plurality of trenches;
etching the Ru layer over the first liner layer and within the recess of each of the plurality of trenches; and
planarizing the IC structure.
9. The method according to claim 8 , the providing the IC structure further comprising a second liner layer formed over the first liner layer.
10. The method according to claim 9 , the planarizing the IC structure comprising performing a CMP of the dielectric layer, the first liner layer, the second liner layer, and the Ru layer.
11. The method according to claim 8 , the first liner layer comprising tantalum nitride, and the second liner layer comprising tantalum.
12. The method according to claim 8 , the etching the Ru layer comprising performing a wet etch.
13. The method according to claim 8 , the planarizing the IC structure comprising performing a chemical mechanical planarization (CMP) of the dielectric layer, the first liner layer, and the Ru layer.
14. The method according to claim 8 , the removing the Cu layer to a top surface of the Ru layer comprising performing chemical mechanical planarization.
15. A method for Back-End-Of-Line interconnect formation, the method comprising:
providing an integrated circuit (IC) structure comprising:
an ultra-low-k (ULK) dielectric layer formed over a substrate, the ULK dielectric layer having a plurality of trenches formed therein;
a first liner layer formed over the ULK dielectric layer;
a ruthenium (Ru) layer formed over the first liner layer; and
a copper (Cu) layer formed over the Ru layer, wherein at least a portion of the dielectric layer, at least a portion of the first liner layer, and at least a portion of the Ru layer are disposed between each portion of the Cu layer and the substrate;
removing the Cu layer to a top surface of the Ru layer by chemical mechanical planarization (CMP);
removing the Cu layer to form a recess within each of the plurality of trenches;
etching the Ru layer over the first liner layer and within the recess of each of the plurality of trenches; and
planarizing the IC structure.
16. The method according to claim 15 , the providing the IC structure further comprising a second liner layer formed over the first liner layer.
17. The method according to claim 16 , the planarizing the IC structure comprising performing a CMP of the dielectric layer, the first liner layer, the second liner layer, and the Ru layer.
18. The method according to claim 15 , the first liner layer comprising tantalum nitride, and the second liner layer comprising tantalum.
19. The method according to claim 15 , the etching the Ru layer comprising performing a wet etch.
20. The method according to claim 15 , the planarizing the IC structure comprising performing a CMP of the dielectric layer, the first liner layer, and the Ru layer.