HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE

1 . A semiconductor structure, comprising:

a field effect transistor (FET) including a channel in a substrate;

a heavily doped region in the substrate;

an undoped or lightly doped intermediate layer on the heavily doped region; and

source and drain regions of the FET on the intermediate layer,

wherein the intermediate layer is between the channel and the source and drain regions; and

the intermediate layer is between the heavily doped region and the source and drain regions.

2 . The semiconductor structure of claim 1 , wherein the intermediate layer comprises undoped or lightly doped silicon.

3 . The semiconductor structure of claim 1 , the intermediate layer prevents the heavily doped region from contacting or overlapping the source and drain regions.

4 . The semiconductor structure of claim 1 , wherein a portion of the intermediate layer that is closest to the gate is transversely spaced apart from a vertical edge of the gate.

5 . The semiconductor structure of claim 1 , further comprising extension regions that extend from under edges of the gate to the source and drain regions.

6 . The semiconductor structure of claim 5 , wherein there is a gap between a lowermost edge of the extension regions and an uppermost edge of the heavily doped region.

7 . The semiconductor structure of claim 1 , wherein the heavily doped region comprises a heavily doped well that affects a threshold voltage, short channel effects, and gate induced drain leakage of the FET.

8 . The semiconductor structure of claim 1 , wherein the intermediate layer reduces gate induced drain leakage by forming a gap region of about 2 nm to about 10 nm between the heavily doped region and the source and drain regions.

9 . A semiconductor structure, comprising:

a heavily doped region in a substrate;

an undoped silicon layer over the heavily doped region;

a gate of a field effect transistor (FET) on the undoped silicon layer, wherein a channel of the FET is in the undoped silicon layer, and wherein the gate comprises a gate stack including a gate dielectric formed on the undoped silicon layer and a gate electrode formed over the gate dielectric;

spacers composed of nitride on sidewalls of the gate stack;

recesses adjacent the channel and the heavily doped region, wherein sidewalls of the recesses are laterally offset from the spacers;

an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and

source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.

10 . The semiconductor structure of claim 9 , wherein:

the heavily doped region comprises a heavily doped well in the substrate; and

the undoped silicon layer containing the channel is on the heavily doped well.

11 . The semiconductor structure of claim 10 , further comprising ultra shallow junction (USJ) extension regions under edges of the gate, wherein the heavily doped well sits under the gate below the USJ extension regions.

12 . The semiconductor structure of claim 11 , wherein the USJ extension regions have a depth less than a thickness of the undoped silicon layer.

13 . The semiconductor structure of claim 12 , further comprising:

silicide spacers on sidewalls of the first spacers, wherein the silicide spacers mask portions of the USJ extension regions adjacent the gate;

a first silicide region at an exposed portion of the gate electrode; and

second silicide regions at the source and drain regions wherein the second silicide regions extend deeper than the USJ extension regions and into the source and drain regions.

14 . The semiconductor structure of claim 9 , further comprising:

isolation trenches in the undoped silicon layer and the heavily doped region; and

doped portions of the substrate at bases of the isolation trenches;

wherein the gate is formed between the isolation trenches; and

the isolation trenches are filled with isolation material.

15 . The semiconductor structure of claim 9 , wherein the gate stack further comprises a gate metal on the gate dielectric with the gate electrode being on the gate metal.

16 . A semiconductor structure, comprising:

a first layer on a substrate, wherein the first layer has a first dopant concentration;

a second layer on the first layer, wherein the second layer has a second dopant concentration less than the first dopant concentration;

a gate of a field effect transistor (FET) on the second layer;

spacers composed of nitride on sidewalls of the gate;

a third layer on surfaces of the substrate, the first layer and the second layer, wherein a third dopant concentration of the third layer is less than the first dopant concentration;

a source and drain regions on the third layer; and

extension regions in the second layer under edges of the gate.

17 . The semiconductor structure of claim 16 , wherein:

a channel of the FET is comprised in a portion of the second layer;

a deep well is comprised in a portion of the first layer; and

the third layer provides a gap region between the deep well and the source and drain regions.

18 . The semiconductor structure of claim 16 , wherein:

the second layer is an undoped silicon layer; and

a channel of the FET is in the undoped silicon layer.

19 . The semiconductor structure of claim 18 , wherein a top surface of the source and drain regions is at a same level as a top surface of the undoped silicon layer.

20 . The semiconductor structure of claim 16 , wherein:

the third dopant concentration is less than the first dopant concentration by at least three orders of magnitude;

the first layer and the third layer comprise p-type dopant;

the source and drain regions comprise n-type dopant;

the substrate is undoped or comprises p-type dopant; and

the second layer is undoped or comprises p-type dopant.