Elongated bump structures in package structure
A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.
1. A package structure, comprising:
a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar, wherein L is different from W, wherein the bump structure further comprises an under bump metallurgy layer; and
a substrate comprising a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region,
wherein the conductive pillar of the chip is attached to the pad region of the substrate via a solder joint region to form an interconnection between the conductive pillar and the pad region,
wherein the solder joint region contacts a center of a major top surface of the conductive pillar along the long axis of the conductive pillar,
wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis; and
wherein L is greater than d1, and W is less than d2.
2. The package structure of claim 1 , wherein the mask layer is formed of a solder resist material layer.
3. The package structure of claim 1 , wherein the conductive pillar comprises copper or copper alloy.
4. The package structure of claim 1 , wherein the long axis of the conductive pillar is perpendicular to an edge of the chip.
5. The package structure of claim 1 , wherein the long axis of the conductive pillar is along a direction toward a central area of the chip.
6. The package structure of claim 1 , wherein the difference between L and d1 is greater than 20 μm.
7. The package structure of claim 1 , wherein the difference between d2 and W is greater than 2 μm.
8. The package structure of claim 1 , wherein d1 is substantially equal to d2.
9. A package structure, comprising:
a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar, wherein the bump structure further comprises an under bump metallurgy layer; and
a substrate comprising a mask layer overlying the substrate and having an opening, and a conductive region filling the opening of the mask layer and protruding from a top surface of the mask layer;
wherein the conductive pillar of the chip is attached to the conductive region of the substrate through a solder joint region to form an interconnection between the conductive pillar and the conductive region,
wherein the solder joint region contacts a center of a major top surface of the conductive pillar along the long axis of the conductive pillar,
wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis; and
wherein L is different from W, L is greater than d1, and W is less than d2.
10. The package structure of claim 9 , wherein the mask layer is formed of a solder resist material layer.
11. The package structure of claim 9 , wherein the conductive pillar comprises copper or copper alloy.
12. The package structure of claim 9 , wherein the long axis of the conductive pillar is perpendicular to an edge of the chip.
13. The package structure of claim 9 , wherein the long axis of the conductive pillar is along a direction toward a central area of the chip.
14. The package structure of claim 9 , wherein the difference between L and d1 is greater than 20 μm.
15. The package structure of claim 9 , wherein the difference between d2 and W is greater than 2 μm.
16. The package structure of claim 9 , wherein d1 is substantially equal to d2.
17. A method of forming a package structure, comprising:
forming a bump structure on a semiconductor device, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar, L being different from W, wherein the bump structure further comprises an under bump metallurgy layer;
forming a solder resist layer on a package substrate having a pad region,
forming an opening in the solder resist layer, wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis, and wherein L is greater than d1, and W is less than d2; and
attaching the conductive pillar of the semiconductor device to the pad region of the package substrate via a solder joint region to form an interconnection between the conductive pillar and the pad region, the solder joint region contacting a center of a major top surface of the conductive pillar along the long axis of the conductive pillar.
18. The method of claim 17 , further comprising forming a solder layer on at least one of the conductive pillar and the pad region.