Heterogeneous integration of group III nitride on silicon for advanced integrated circuits
Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.
1. A method of integrating a Group III nitride material and silicon, said method comprising:
providing a structure comprising, from bottom to top, a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer;
forming an opening through the blanket layer of dielectric material, and the Group III nitride material layer to expose a portion of the uppermost surface of the (111) silicon layer;
performing an oxidation process to form an oxide plug within said exposed portion of the (111) silicon layer, wherein a bottommost surface of the oxide plug contacts the uppermost surface of the (100) silicon layer;
forming a conformal dielectric material liner atop remaining portions of the blanket layer of dielectric material and within said opening;
removing horizontal portions of said conformal dielectric material liner and a portion of said oxide plug to expose a portion of the uppermost surface of the (100) silicon layer;
forming an epitaxial semiconductor material on said exposed portion of the uppermost surface of the (100) silicon layer; and
removing portions of the epitaxial semiconductor material, and remaining portions of the blanket layer of dielectric material to expose the uppermost surface of remaining portions of the Group III nitride material layer.
2. The method of claim 1 , further comprising a buried insulator layer located beneath and in contact with a bottommost surface of the (100) silicon layer, and a semiconductor substrate located beneath and in contact with a bottommost surface of the buried insulator layer.
3. The method of claim 2 , wherein said Group III nitride material layer is formed on said uppermost surface of the (111) silicon layer by metalorganic chemical vapor deposition.
4. The method of claim 3 , wherein said metalorganic chemical vapor deposition comprises introducing a Group III-containing precursor and a nitride precursor into a reactor chamber and depositing said precursors at a temperature of 850° C. or greater.
5. The method of claim 1 , wherein a portion of said oxide plug and a portion of said conformal dielectric material liner remain within said opening and form a composite dielectric spacer, wherein a bottommost surface of the remaining portion of said oxide plug contacts an uppermost surface of said (100) silicon layer.
6. A semiconductor structure comprising:
a (100) silicon layer having an uppermost surface;
a buried insulator layer located on the uppermost surface of the (100) silicon layer;
a (111) silicon layer located on an uppermost surface of the buried insulator layer;
a patterned Group III nitride material layer located on an uppermost surface of the (111) silicon layer; and
an epitaxial semiconductor material layer located within an opening in said patterned Group III nitride material layer, wherein said epitaxial semiconductor material layer has a bottommost surface in direct contact with the uppermost surface of the (111) silicon layer, and an uppermost surface that is coplanar within the uppermost surface of said patterned Group III nitride material layer, and wherein sidewall surfaces of the epitaxial semiconductor material layer are separated from sidewall surfaces of said patterned Group III nitride material layer by a dielectric spacer.