Vertical integration of CMOS electronics with photonic devices

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing an SOI substrate including a plurality of silicon-based devices;

providing a compound semiconductor substrate including a plurality of photonic devices;

dicing the compound semiconductor substrate to provide a plurality of photonic dies, each die including one or more of the plurality of photonics devices;

providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices;

mounting the plurality of photonic dies on predetermined portions of the assembly substrate;

aligning the SOI substrate and the assembly substrate;

joining the SOI substrate and the assembly substrate to form a composite substrate structure; and

removing at least the base layer of the assembly substrate from the composite substrate structure.

2. The method of claim 1 wherein the plurality of silicon-based devices comprise CMOS devices.

3. The method of claim 1 wherein the plurality of silicon-based devices comprise at least one of a detector, a CCD, logic circuits, emitter coupled logic circuits, BiCMOS circuits, NMOS circuits, PMOS circuits, or other silicon-based devices or circuits.

4. The method of claim 1 wherein the compound semiconductor substrate comprises a III-V wafer.

5. The method of claim 1 wherein the compound semiconductor substrate comprises a II-VI wafer.

6. The method of claim 1 wherein the plurality of photonic devices include at least one of a laser, a detector, or a modulator.

7. The method of claim 6 wherein the plurality of photonic devices further include at least one of imaging optics, magnetic materials, birefringent materials, or non-linear optical materials.

8. The method of claim 1 wherein the compound semiconductor substrate further includes electronic devices.

9. The method of claim 8 wherein the electronic devices include at least one of HBTs, HEMTs, or FETs.

10. The method of claim 1 wherein the plurality of CMOS devices comprise silicon-based CMOS devices.

11. The method of claim 1 wherein the plurality of CMOS devices comprise silicon/germanium CMOS devices.

12. The method of claim 1 wherein the plurality of CMOS devices comprise at least one of a detector, a CCD, logic circuits, emitter coupled logic circuits, BiCMOS circuits, SiGe BiCMOS circuits, NMOS circuits, or PMOS circuits.

13. The method of claim 1 wherein providing the assembly substrate comprises:

oxidizing a silicon substrate;

implanting the oxidized silicon substrate to form an implant region; and

patterning the implanted substrate to form the predetermined portions.

14. The method of claim 13 wherein implanting the oxidized silicon substrate comprises implanting at least one of hydrogen or helium.

15. The method of claim 13 wherein removing at least the base layer of the assembly substrate comprises annealing the composite substrate structure to split the assembly substrate at the implant region.

16. The method of claim 13 wherein removing at least the base layer of the assembly substrate comprises lapping a portion of the assembly substrate.

17. A method of growing a compound semiconductor structure on a silicon-based substrate, the method comprising:

providing an SOI base wafer having a bonding surface;

providing a seed wafer;

dicing the seed wafer to provide a plurality of seed dies;

providing a template wafer including a plurality of CMOS devices;

mounting the plurality of seed dies on the template wafer;

bonding the template wafer to the SOI base wafer, wherein the plurality of seed dies are joined to the bonding surface of the SOI base wafer;

removing at least a portion of the template wafer;

exposing at least a portion of a surface of the plurality of seed dies; and

growing the compound semiconductor structure on the exposed seed dies.

18. The method of claim 17 wherein growing the compound semiconductor structure comprises performing an epitaxial growth process.

19. The method of claim 17 wherein the SOI base wafer comprises doped regions associated with transistors.

20. The method of claim 17 wherein the seed wafer comprises a III-V wafer.

21. The method of claim 17 wherein mounting the plurality of seed dies on the template wafer comprises mounting the plurality of seed dies on predetermined regions of the template wafer.

22. The method of claim 17 wherein providing the template wafer comprises:

oxidizing a silicon substrate;

implanting a dopant into the oxidized silicon substrate to form an implant region; and

patterning the implanted substrate to form the predetermined portions.

23. The method of claim 22 wherein the implant region ranges from about 0.1 μm to about 5 μm from a surface of the template wafer.

24. The method of claim 23 wherein removing at least a portion of the template wafer comprises:

annealing the bonded template wafer and SOI base wafer; and

splitting the template wafer at the implant region, wherein the plurality of CMOS devices remain bonded to the SOI base wafer.

25. The method of claim 24 further comprising performing a CMP process after splitting the template wafer.

26. The method of claim 17 further comprising at least one of fabricating gate metals or fabricating transistor interconnects after growing the compound semiconductor structure.

27. The method of claim 17 wherein exposing at least a portion of a surface of the plurality of seed dies comprises patterning and etching portions of the template wafer.

28. The method of claim 17 wherein bonding the template wafer to the SOI base wafer comprises forming at least one of a semiconductor-semiconductor bond or a metal assisted semiconductor bond.

29. The method of claim 28 wherein the metal assisted semiconductor bond comprises InPd.

30. The method of claim 17 wherein the plurality of CMOS devices comprise silicon-based CMOS devices.

31. The method of claim 17 wherein the plurality of CMOS devices comprise silicon/germanium CMOS devices.

32. The method of claim 17 wherein the plurality of CMOS devices comprise at least one of a detector, a CCD, logic circuits, emitter coupled logic circuits, BiCMOS circuits, NMOS circuits, or PMOS circuits.