Automated test platform utilizing segmented data sequencers to provide time controlled test sequences to device under test
View Patent ↗A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment.
1. A segmented subsystem, for use within an automated test platform, comprising:
a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment, wherein the first subsystem segment is at least one of a first instrument card and a first digital signal processing card, and wherein the first subsystem segment includes a first DMA engine configured to allow the first subsystem segment to read data from and/or write data to a remote memory system;
one or more PCIe based event fabrics including one or more PCIe switches, the one or more PCIe switches configured to interface one or more CPU subsystems with at least one of the first instrument card and the first digital signal processing card, wherein at least one of the first instrument card and the first digital signal processing card is separate from each of the one or more PCIe switches; and
a second subsystem segment including a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment, wherein the second subsystem segment is at least one of a second instrument card and a second digital signal processing card, wherein the first subsystem segment is further configured to provide one or more variable input signals to a device under test for a first defined period of time based on a timing signal, wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the first defined period of time, wherein after expiration of the first defined period of time, the first subsystem segment is further configured to provide one or more variable input signals to the device under test for a second defined period of time based on a timing signal, and wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the second defined period of time.
2. The segmented subsystem of claim 1 wherein the remote memory system is accessible by the one or more CPU subsystems included within the automated test platform.
3. The segmented subsystem of claim 1 wherein the second subsystem segment includes a second DMA engine configured to allow the second subsystem segment to read data from and/or write data to a remote memory system.
4. The segmented subsystem of claim 3 wherein the remote memory system is accessible by the one or more CPU subsystems included within the automated test platform.
5. The segmented subsystem of claim 1 further comprising at least a third subsystem segment including at least a third data sequencer configured to coordinate the execution of one or more instructions within the at least a third subsystem segment.
6. The segmented subsystem of claim 5 wherein the at least a third subsystem segment includes at least a third DMA engine configured to allow the at least a third subsystem segment to read data from and/or write data to a remote memory system.
7. The segmented subsystem of claim 6 wherein the remote memory system is accessible by the one or more CPU subsystems included within the automated test platform.
8. The segmented subsystem of claim 1 wherein at least one of the first and second subsystem segment is a segmented instrument subsystem.
9. The segmented subsystem of claim 8 wherein the segmented instrument subsystem includes instrument hardware configured to interface with one or more devices under test.
10. The segmented subsystem of claim 1 wherein at least one of the first and second subsystem segment includes a PCIe interface configured to couple the subsystem segment with the one or more PCIe-based event fabrics.
11. The segmented subsystem of claim 10 wherein at least one of the one or more PCIe-based event fabrics include a PCIe backplane.
12. A segmented subsystem, for use within an automated test platform, comprising:
a first subsystem segment, wherein the first subsystem segment is at least one of a first instrument card and a first digital signal processing card, including:
a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment, and a first DMA engine configured to allow the first subsystem segment to read data from and/or write data to a remote memory system;
one or more PCIe based event fabrics including one or more PCIe switches, the one or more PCIe switches configured to interface one or more CPU subsystems with at least one of the first instrument card and the first digital signal processing card, wherein at least one of the first instrument card and the first digital signal processing card is separate from each of the one or more PCIe switches; and
a second subsystem segment, wherein the second subsystem segment is at least one of a second instrument card and a second digital signal processing card, including:
a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment, and a second DMA engine configured to allow the second subsystem segment to read data from and/or write data to the remote memory system, wherein the first subsystem segment is further configured to provide one or more variable input signals to a device under test for a first defined period of time based on a timing signal, wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the first defined period of time, wherein after expiration of the first defined period of time, the first subsystem segment is further configured to provide one or more variable input signals to the device under test for a second defined period of time based on a timing signal, and wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the second defined period of time.
13. The segmented subsystem of claim 12 further comprising at least a third subsystem segment including: at least a third data sequencer configured to coordinate the execution of one or more instructions within the at least a third subsystem segment, and at least a third DMA engine configured to allow the at least a third subsystem segment to read data from and/or write data to a remote memory system.
14. A segmented instrument subsystem, for use within an automated test platform, comprising:
a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment, wherein the first subsystem segment is at least one of a first instrument card and a first digital signal processing card, and wherein the first subsystem segment includes a first DMA engine configured to allow the first subsystem segment to read data from and/or write data to a remote memory system;
a second subsystem segment including a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment, wherein the second subsystem segment is at least one of a second instrument card and a second digital signal processing card;
instrument hardware configured to interface with one or more devices under test, wherein at least one of the first instrument card and the first digital signal processing card includes the instrument hardware; and
a PCIe interface configured to couple the segmented instrument subsystem with one or more PCIe-based event fabrics, the one or more PCIe based event fabrics including one or more PCIe switches, the one or more PCIe switches configured to interface one or more CPU subsystems with at least one of the first instrument card and the first digital signal processing card, wherein at least one of the first instrument card and the first digital signal processing card is separate from each of the one or more PCIe switches, wherein the first subsystem segment is further configured to provide one or more variable input signals to a device under test for a first defined period of time based on a timing signal, wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the first defined period of time, wherein after expiration of the first defined period of time, the first subsystem segment is further configured to provide one or more variable input signals to the device under test for a second defined period of time based on a timing signal, and wherein the second subsystem segment is further configured to monitor one or more output signals provided by the device under test resulting from the one or more variable input signals provided by the first subsystem segment to the device under test during the second defined period of time.
15. The segmented instrument subsystem of claim 14 wherein the second subsystem segment includes a second DMA engine configured to allow the second subsystem segment to read data from and/or write data to a remote memory system.