IP Library Granted Patent US 9,184,094
Granted Patent B1
US 9,184,094 · App. 13/750,163 · Granted Nov 10, 2015

Method and system for forming a membrane over a cavity

Inventor: Elton Marchena (Albuquerque, NM)
Assignee: Skorpios Technologies, Inc.
H01L21/7806H01L21/76251H01L21/76254H01L33/0079H01L21/764
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Quick Facts
Patent No.
US 9,184,094
App. No.
13/750,163
Granted
Nov 10, 2015
Kind
B1
Abstract

A method of fabricating a semiconductor device includes providing an assembly substrate including a split plane defining a handle region and a transfer region, a film layer coupled to the transfer region, and one or more active devices coupled to the film layer. The method also includes providing a device substrate including one or more bonding regions and joining the assembly substrate to the device substrate. The method further includes splitting the assembly substrate to remove the handle region.

Claims (14)

1. A method of fabricating a semiconductor device, the method comprising:

providing an assembly substrate including a split plane defining a handle region and a transfer region, a film layer coupled to the transfer region, and one or more active devices coupled to the film layer;

providing a device substrate including one or more bonding regions, wherein the one or more bonding regions include one or more receptor sites;

joining the assembly substrate to the device substrate, wherein joining the assembly substrate to the device substrate comprises directly bonding the film layer to a portion of the device substrate and directly bonding the one or more active devices to the one or more receptor sites of the device substrate, and wherein at least a portion of the film layer is suspended over a cavity formed between the one or more active devices directly bonded to the one or more receptor sites and the portion of the device substrate directly bonded to the film layer; and

splitting the assembly substrate to remove the handle region.

2. The method of claim 1 wherein the one or more active devices comprises III-V optical or electronic devices.

3. The method of claim 1 wherein the assembly substrate comprises a silicon substrate.

4. The method of claim 1 further comprising fabricating one or more additional layers coupled to the transfer region of the assembly substrate.

5. The method of claim 1 wherein the split plane comprises an ion implanted region.

6. The method of claim 1 wherein the film layer comprises one or more oxide or nitride layers.

7. The method of claim 1 wherein the device substrate comprises a silicon substrate.

8. The method of claim 1 wherein

the transfer region and the film layer are characterized by a combined thickness of about 100 nm to 2 microns.

9. The method of claim 1 wherein joining the assembly substrate to the device substrate comprises forming a bonding layer on the portion of the device substrate and bonding the film layer to the bonding layer.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 22, 2017
From: PACIFIC WESTERN BANK
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 044751/0469 →
SECURITY INTEREST Recorded Oct 23, 2017
From: SKORPIOS TECHNOLOGIES, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 044272/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2013
From: MARCHENA, ELTON
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 030174/0320 →
Continuity (1)
Provisional Application 61590887 · Jan 26, 2012