FETCHING INSTRUCTIONS OF A LOOP ROUTINE
In one aspect, a processor is configured to store instructions fetched from a program memory in an instruction queue, determine that an instruction to be decoded defines a beginning of a loop routine, and determine whether the instruction is stored in the instruction queue. In response to determining that the instruction is stored in the instruction queue, the processor disables fetching of instructions from the program memory, fetches instructions of the loop routine from the instruction queue, and stores the instructions of the loop routine in an instruction register. In response to determining that the instruction is not stored in the instruction queue, the processor fetches the instruction from the program memory, stores the instruction in the instruction queue, and stores the instruction in the instruction register.
1 . A method comprising:
storing instructions fetched from a program memory in an instruction queue;
determining that an instruction to be decoded defines a beginning of a loop routine;
determining whether the instruction is stored in the instruction queue;
in response to determining that the instruction is stored in the instruction queue:
disabling fetching of instructions from the program memory,
fetching instructions of the loop routine from the instruction queue, and
storing the instructions of the loop routine in an instruction register; and
in response to determining that the instruction is not stored in the instruction queue:
fetching the instruction from the program memory,
storing the instruction in the instruction queue, and
storing the instruction in the instruction register.
2 . The method of claim 1 , wherein storing instructions fetched from the program memory in the instruction queue comprises:
storing instructions fetched from the program memory in a first in, first out (FIFO) queue.
3 . The method of claim 1 , wherein storing instructions fetched from the program memory in the instruction queue comprises:
storing instructions that are skipped as a result of a branch or a jump.
4 . The method of claim 1 , wherein determining that the instruction to be decoded defines the beginning of the loop routine comprises:
determining that a decoded instruction defines an ending point of the loop routine; and
determining that a number of iterations of the loop routine remaining has not reached zero.
5 . The method of claim 1 , wherein determining that the instruction to be decoded defines the beginning of the loop routine comprises:
receiving a memory address associated with a result of an executed instruction; and
determining that the memory address occurs earlier than a memory address associated with the executed instruction.
6 . The method of claim 1 , wherein in response to determining that the instruction is stored in the instruction queue, the method further comprises:
determining that the loop routine has been exited; and
re-enabling fetching of instructions from the program memory.
7 . The method of claim 1 , wherein in response to determining that the instruction is not stored in the instruction queue, storing the instruction in the instruction queue and storing the instruction in the instruction register comprises storing the instruction in the instruction register concurrently with the storing of the instruction in the instruction queue.
8 . An apparatus comprising:
an instruction queue;
an instruction register; and
a controller configured to:
store instructions fetched from a program memory in the instruction queue;
determine that an instruction to be decoded defines a beginning of a loop routine;
determine whether the instruction is stored in the instruction queue;
in response to determining that the instruction is stored in the instruction queue:
disable fetching of instructions from the program memory,
fetch instructions of the loop routine from the instruction queue, and
store the instructions of the loop routine in the instruction register; and
in response to determining that the instruction is not stored in the instruction queue:
fetch the instruction from the program memory,
store the instruction in the instruction queue, and
store the instruction in the instruction register.
9 . The apparatus of claim 8 , wherein the controller is configured to store instructions fetched from the program memory in a first in, first out (FIFO) queue.
10 . The apparatus of claim 8 , wherein the controller is configured to store instructions that are skipped as a result of a branch or a jump.
11 . The apparatus of claim 8 , wherein the controller is configured to:
determine that a decoded instruction defines an ending point of the loop routine; and
determine that a number of iterations of the loop routine remaining has not reached zero.
12 . The apparatus of claim 8 , wherein the controller configured to:
receive a memory address associated with a result of an executed instruction; and
determine that the memory address occurs earlier than a memory address associated with the executed instruction.
13 . The apparatus of claim 8 , wherein in response to determining that the instruction is stored in the instruction queue, the controller is further configured to:
determine that the loop routine has been exited; and
re-enable fetching of instructions from the program memory.
14 . The apparatus of claim 8 , wherein in response to determining that the instruction is not stored in the instruction queue, the controller is configured to store the instruction in the instruction register concurrently with the storing of the instruction in the instruction queue.
15 . A system comprising:
a program memory; and
a processor configured to:
store instructions fetched from the program memory in an instruction queue;
determine that an instruction to be decoded defines a beginning of a loop routine;
determine whether the instruction is stored in the instruction queue;
in response to determining that the instruction is stored in the instruction queue:
disable fetching of instructions from the program memory,
fetch instructions of the loop routine from the instruction queue, and
store the instructions of the loop routine in an instruction register; and
in response to determining that the instruction is not stored in the instruction queue:
fetch the instruction from the program memory,
store the instruction in the instruction queue, and
store the instruction in the instruction register.
16 . The system of claim 15 , wherein the processor is configured to store instructions fetched from the program memory in a first in, first out (FIFO) queue.
17 . The system of claim 15 , wherein the processor is configured to store instructions that are skipped as a result of a branch or a jump.
18 . The system of claim 15 , wherein the processor is configured to:
determine that a decoded instruction defines an ending point of the loop routine; and
determine that a number of iterations of the loop routine remaining has not reached zero.
19 . The system of claim 15 , wherein the processor is configured to:
receive a memory address associated with a result of an executed instruction; and
determine that the memory address occurs earlier than a memory address associated with the executed instruction.
20 . The system of claim 15 , wherein in response to determining that the instruction is stored in the instruction queue, the processor is further configured to:
determine that the loop routine has been exited; and
re-enable fetching of instructions from the program memory.
21 . The system of claim 15 , wherein in response to determining that the instruction is not stored in the instruction queue, the processor is configured to store the instruction in the instruction register concurrently with the storing of the instruction in the instruction queue.