Methods of forming reverse side engineered III-nitride devices
Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.
1. A method of forming a device, comprising:
providing a mother wafer;
forming a stack of III-nitride layers on the mother wafer, wherein the forming of the stack includes forming a channel layer with a 2DEG channel therein, the stack of III-nitride layers having an obverse face opposite to the mother wafer and a reverse face opposite the obverse face;
forming a source and a drain on the obverse face of the stack of III-nitride layers, each of the source and the drain being in electrical contact with the channel layer, wherein the drain is spaced apart from the source such that a first region of the device is between the source and the drain;
exposing the reverse face of the stack of III-nitride layers in the first region of the device by removing at least the mother wafer from the first region of the device; and
forming, in the first region of the device, a passivation layer comprising dielectric material, the passivation layer being formed on the exposed reverse face of the stack of III-nitride layers, in direct contact with the stack of III-nitride layers in the first region of the device.
2. The method of claim 1 , wherein:
the stack of III-nitride layers includes a barrier layer on a first side of the channel layer and a spacer layer on a second side of the channel layer;
the spacer layer includes an etch stop layer; and
the removing step etches to the etch stop layer.
3. The method of claim 1 , wherein the mother wafer is a silicon mother wafer.
4. The method of claim 1 , wherein the forming of the stack of III-nitride layers comprises forming a nucleation layer on the mother wafer.
5. The method of claim 4 , further comprising removing the nucleation layer in the first region of the device.
6. The method of claim 1 , further comprising fabricating one of a diode or a transistor in the stack of III-nitride layers.
7. The method of claim 1 , wherein the dielectric material comprises silicon nitride, silicon dioxide, silicon oxynitride, silicon oxide, or alumina.
8. The method of claim 1 , wherein the dielectric material comprises polymide, benzocyclobutene, SU8, or an organic dielectric material.
9. The method of claim 1 , further comprising depositing an insulator material on the obverse face.