Semiconductor device assembly utilizing a DBC substrate
A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.
1. An assembly comprising:
first and second semiconductor devices, each of said first and second semiconductor devices comprising:
first and second conductive layers insulated from one another, said first conductive layer having a depression therein and a rim at least partially surrounding a bottom surface of said depression;
a semiconductor die situated in said depression and having an electrode electrically connected to said bottom surface of said depression;
a support substrate including a patterned conductive layer electrically connecting said first semiconductor device and said second semiconductor device, said first and second semiconductor devices each being electrically and mechanically connected to said patterned conductive layer.
2. The assembly of claim 1 , wherein said patterned conductive layer is electrically connecting said rim of said first semiconductor device and said rim of said second semiconductor device.
3. The assembly of claim 1 , wherein said support substrate further comprises a bottom conductive layer that is insulated from said patterned conductive layer.
4. The assembly of claim 1 , a heat sink or plate mechanically and thermally connected to said second conductive layer of each of said first and second semiconductor devices.
5. The assembly of claim 1 , comprising an EMI screening plate situated over said first and second semiconductor devices, said EMI screening plate electrically connected to said first and second semiconductor devices through said patterned conductive layer.
6. The assembly of claim 1 , wherein another electrode of said first semiconductor device and another electrode of said second semiconductor device are each electrically and mechanically connected to said patterned conductive layer.
7. The assembly of claim 1 , wherein said first and second conductive layers of each of said first and second semiconductor devices are on a common insulation layer.
8. The assembly of claim 1 , comprising a first terminal electrically and mechanically connected to said second conductive layer of said first semiconductor device and a second terminal electrically and mechanically connected to said patterned conductive layer.
9. The assembly of claim 1 , comprising an integrated circuit mounted atop and electrically connected to said first and second semiconductor devices.
10. The assembly of claim 1 , wherein said support substrate is a direct bonded copper (DBC) substrate.
11. An assembly comprising:
a semiconductor device including first and second conductive layers insulated from one another, said first conductive layer having a depression therein and a rim at least partially surrounding a bottom surface of said depression;
a semiconductor die of said semiconductor device situated in said depression and having an electrode electrically connected to said bottom surface of said depression;
a support substrate including a patterned conductive layer electrically and mechanically connected to said semiconductor device;
an integrated circuit (IC) electrically and mechanically connected to said second conductive layer of said semiconductor device.
12. The assembly of claim 11 , wherein said IC is electrically connected to said semiconductor die through wirebonds.
13. The assembly of claim 11 comprising wirebonds electrically connecting said IC to said semiconductor device through said second conductive layer.
14. The assembly of claim 11 , wherein said IC is electrically connected to said second conductive layer through ball contacts.
15. The assembly of claim 11 , wherein said IC is a prepackaged IC having IC terminals electrically and mechanically connected to said second conductive layer.
16. The assembly of claim 11 , wherein said IC is a control IC of said semiconductor device.
17. The assembly of claim 11 , wherein said IC is configured to measure a voltage drop across a shunt of said semiconductor device.
18. The assembly of claim 11 comprising an external interface terminal electrically and mechanically connected to said second conductive layer.
19. The assembly of claim 11 , wherein said first and second conductive layers are on an insulation layer, a shunt in said insulation layer electrically connecting said first and second conductive layers.
20. The assembly of claim 11 , wherein said rim of said semiconductor device is electrically and mechanically connected to said patterned conductive layer.