Reverse program and erase cycling algorithms

1. A method of erasing a programmable impedance element, the method comprising:

a) receiving an erase command to be executed on the programmable impedance element;

b) performing an erase operation on the programmable impedance element in response to the erase command;

c) determining if the erase operation successfully erased the programmable impedance element; and

d) performing a program operation for erasing the programmable impedance element in response to the erase operation failing to successfully erase the programmable impedance element.

2. The method of claim 1 , wherein:

a) the program operation comprises a plurality of program operations; and

b) the erase operation comprises a plurality of erase operations.

3. The method of claim 1 , wherein the determining if the erase operation successfully erased comprises:

a) measuring a cell resistance of the programmable impedance element; and

b) comparing the cell resistance against a predetermined resistance to determine if the cell resistance is greater than the predetermined resistance.

4. The method of claim 1 , wherein the performing the erase operation comprises decreasing a cell resistance of the programmable impedance element.

5. The method of claim 1 , wherein the performing the program operation comprises increasing a cell resistance of the programmable impedance element.

6. The method of claim 1 , wherein the programmable impedance element is part of a memory array having a plurality of memory cells, wherein each of the memory cells comprises:

a) an active electrode of the programmable impedance element being coupled to a bit line; and

b) a transistor having a drain coupled to the inert electrode of the programmable impedance element, a gate coupled to a word line, and a source coupled to a source line.

7. The method of claim 1 , wherein the programmable impedance element comprises:

a) an inert electrode coupled to a first side of a solid electrolyte;

b) an active electrode coupled to a second side of the solid electrolyte, wherein the programmable impedance element is programmed by formation of a conductive path between the active and inert electrodes; and

c) a plurality of mobile elements derived from the active electrode, wherein the plurality of mobile elements are reduced in the solid electrolyte to form the conductive path.

8. The method of claim 7 , wherein:

a) the conductive path in the programmable impedance element is formed by application of a first voltage across the active and inert electrodes, the conductive path remaining once formed after the first voltage is removed; and

b) at least a portion of the conductive path is dissolved to erase the programmable impedance element by application of a second voltage across the active and inert electrodes.

9. The method of claim 2 , wherein each of the plurality of program operations comprises selecting an option variable for at least one of pulse widths, voltages, and currents.

10. The method of claim 2 , wherein each of the plurality of erase operations comprises selecting an option variable for at least one of pulse widths, voltages, and currents.

11. The method of claim 1 , wherein the programmable impedance element comprises an ion buffer layer (IBL) and an oxide.

12. The method of claim 1 , wherein the programmable impedance element exhibits reverse program/erase behavior.

13. The method of claim 1 , wherein the performing the erase operation comprises incrementing a retry counter.

14. The method of claim 13 , wherein the determining if the erase operation successfully erased comprises comparing the retry counter against a retry limit.

15. The method of claim 14 , wherein the erase operation is determined to have failed to successfully erase the programmable impedance element when the retry counter reaches the retry limit.