Methods of making a high-density nonvolatile memory
View Patent ↗Methods are provided for forming a monolithic three dimensional memory array. An example method includes: (a) forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate; (b) forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors; and (c) forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements. Each of the first plurality of semiconductor elements includes a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer. The third heavily doped layer has a second conductivity type opposite the first conductivity type. Numerous other aspects are provided.
1. A method for forming a monolithic three dimensional memory array, the method comprising:
forming a first plurality of substantially parallel, substantially coplanar conductors above a substrate;
forming a first plurality of semiconductor elements above the first plurality of substantially parallel, substantially coplanar conductors, each of the first plurality of semiconductor elements comprising a first heavily doped layer having a first conductivity type, a second lightly doped layer on and in contact with the first heavily doped layer, and a third heavily doped layer on and in contact with the second lightly doped layer, the third heavily doped layer having a second conductivity type opposite the first conductivity type; and
forming a second plurality of substantially parallel, substantially coplanar conductors above the first plurality of semiconductor elements.
2. The method of claim 1 , wherein forming the first plurality of substantially parallel, substantially coplanar conductors comprises:
depositing a first conductive layer;
patterning and etching the first conductive layer to form the first plurality of substantially parallel, substantially coplanar conductors;
depositing a first dielectric material over and between the first plurality of substantially parallel, substantially coplanar conductors; and
planarizing to expose tops of the first plurality of substantially parallel, substantially coplanar conductors separated by the first dielectric material.
3. The method of claim 2 , wherein forming the first plurality of semiconductor elements comprises:
after planarizing, depositing a first semiconductor layer stack on the first dielectric material and the first plurality of substantially parallel, substantially coplanar conductors;
patterning and etching the first semiconductor layer stack to form the first plurality of semiconductor elements;
depositing a second dielectric material on and between the first plurality of semiconductor elements; and
planarizing to expose tops of the first plurality of semiconductor elements.
4. The method of claim 3 , wherein depositing the first semiconductor layer stack comprises depositing polycrystalline silicon.
5. The method of claim 1 , wherein each of the first plurality of semiconductor elements is pillar-shaped.
6. The method of claim 1 , wherein the third heavily doped layer of each of the first plurality of semiconductor elements is doped by ion implantation.
7. The method of claim 1 , wherein the first heavily doped layer of each of the first plurality of semiconductor elements is doped by in situ doping.
8. The method of claim 1 , further comprising forming a second plurality of semiconductor elements above the second plurality of substantially parallel, substantially coplanar conductors.
9. The method of claim 8 , further comprising forming a third plurality of substantially parallel, substantially coplanar conductors above the second plurality of semiconductor elements.
10. The method of claim 1 , further comprising forming a plurality of first antifuse layers disposed between the first plurality of semiconductor elements and the second plurality of substantially parallel, substantially coplanar conductors.
11. The method of claim 10 , wherein forming the first antifuse layers comprises forming oxide layers.
12. The method of claim 11 , wherein forming oxide layers comprises oxidizing a portion of the third heavily doped layer of each of the first plurality of semiconductor elements.
13. The method of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
14. The method of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.