Power saving techniques for image sensors
View Patent ↗Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block.
1. Image processing circuitry coupled to an image sensor that generates pixel data, comprising:
a plurality of processing blocks that process lines of the pixel data, wherein each of the plurality of processing blocks has a respective clock that is disabled between each line of the pixel data to reduce power consumption, wherein the plurality of processing block comprises:
a first processing block that receives a first input clock enable signal and generates a first output clock enable signal that is different from the first input clock enable signal; and
a second processing block that is different from the first processing block and that receives the first output clock enable signal and generates a second output clock enable signal that is different from the first output clock enable signal, wherein an output of the first processing block is directly connected to an input of the second processing block.
2. The image processing circuitry defined in claim 1 , wherein a first of the plurality of processing blocks is configured to output a second clock enable signal for a second of the plurality of the processing blocks.
3. The image processing circuitry defined in claim 2 , wherein the first of the plurality of processing blocks includes timing control circuitry having a plurality of delay elements, an OR logic gate, and an AND logic gate.
4. The image processing circuitry defined in claim 3 , wherein the OR logic gate has a first input connected to the plurality of delay elements and a second input configured to receive the first clock enable signal, wherein the AND logic gate has a first input connected to an output of the OR logic gate and a second input configured to receive a global continuous clock signal, and wherein the AND logic gate is configured to output a first clock signal for the first processing block.
5. The image processing circuitry defined in claim 4 , wherein the second clock enable signal is provided at an output of the plurality of delay elements.
6. The image processing circuitry defined in claim 4 , wherein the plurality of delay elements are clocked by the first clock signal.
7. The image processing circuitry defined in claim 1 , further comprising timing control delay pipe circuitry that includes a plurality of delay elements, wherein the timing control delay pipe circuitry is configured to receive a line valid signal and to output a first clock enable signal to a first of the plurality of processing blocks.
8. The image processing circuitry defined in claim 7 , wherein the timing control circuitry further includes an OR logic gate having a first input connected to the plurality of delay elements and a second input configured to receive the line enable signal, wherein the OR logic gate is configured to output the first clock enable signal.
9. The image processing circuitry defined in claim 1 , wherein the first processing block generates the first output clock signal by delaying the first input clock signal, and wherein the second processing block generates the second output clock signal by delaying the first output clock signal.
10. A method for reducing power consumption in image processing circuitry coupled to an image sensor that generates pixel data, wherein the image processing circuitry comprises a plurality of sequentially ordered processing blocks, the method comprising:
receiving, at a given processing block of the plurality of processing blocks, a clock enable signal;
with a delay circuit in the given processing block, delaying the clock enable signal at the given processing block to produce a delayed clock enable signal;
sending the delayed clock enable signal directly from the given processing block to an input of a subsequent processing block;
enabling each clock in the plurality of processing blocks while the processing blocks are processing lines of the pixel data; and
disabling each clock during at least a portion of a blanking time between each line of the pixel data.
11. The method defined in claim 10 , wherein enabling each clock in the plurality of processing blocks while the processing blocks are processing lines of the pixel data comprises enabling each clock 1 to 3 cycles before each line of the pixel data is received at the processing block.
12. The method defined in claim 10 , further comprising:
receiving, at timing control delay pipe circuitry, a line enable signal; and
sending, from the timing control delay pipe circuitry to the given processing block, the clock enable signal.
13. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
a pixel array in a substrate; and
an image processor that includes a plurality of processing blocks that receive pixel data from the pixel array, wherein each processing block in the plurality of processing blocks has a different clock that is individually enabled while processing a line of the pixel data and individually disabled between lines of data, wherein the plurality of processing blocks comprise:
a first processing block that includes a plurality of delay elements, wherein the plurality of delay elements is configured to receive a first clock enable signal, delay the first clock enable signal to produce a second clock enable signal, and to output the second clock enable signal;
a second processing block that receives the second clock enable signal directly from an output of the first processing block, and that delays the second clock enable signal to produce a third clock enable signal; and
a third processing block that receives the third clock enable signal directly from an output of the second processing block.
14. The system defined in claim 13 , wherein the image processor includes timing control delay pipe circuitry that includes a plurality of delay elements and a logic gate, wherein the timing control delay pipe circuitry is configured to receive a line valid signal, and wherein the timing control delay pipe circuitry is configured to output the first clock enable signal to the first processing block.
15. The system defined in claim 13 , wherein the first processing block further includes a first logic gate that is configured to receive the first clock enable signal and the second clock enable signal.
16. The system defined in claim 15 , wherein the first processing block further includes a second logic gate that has a first input connected to an output of the first logic gate and a second input configured to receive a continuous clock and wherein the second logic gate is configured to output a first clock for the first processing block.
17. The system defined in claim 13 , wherein the plurality of processing blocks include a defect correction processing block and a scaling processing block.
18. The system defined in claim 13 , wherein a first processing block in the plurality of processing block includes a plurality of delay elements, wherein the plurality of delay elements is configured to receive a first clock enable signal, and wherein the plurality of delay elements is configured to output a second clock enable signal to a second processing block in the plurality of processing blocks.