FIELD STOP STRUCTURE, REVERSE CONDUCTING IGBT SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THE SAME
A field stop structure is disclosed. The field stop structure is divided into a three-dimensional structure by a plurality of trenches formed on a back side of a silicon substrate and hence obtains a greater formation depth in the substrate and can achieve a higher ion activation efficiency. Moreover, a first electrode region of a fast recovered diode (FRD) is formed in the trenches, thereby enabling the integration of a FRD with an insulated gate bipolar transistor (IGBT) device. Methods for forming field stop structure and reverse conducting IGBT semiconductor device are also disclosed.
1 . A field stop structure, formed in a silicon substrate having a first conductivity type, a plurality of trenches being formed on a back side of the silicon substrate, the field stop structure comprising:
a first field stop layer of the first conductivity type located in a portion of the silicon substrate at bottom of the plurality of trenches, the first field stop layer being laterally continuous; and
a plurality of second field stop layers of the first conductivity type, each being located between two adjacent trenches and being joined with the first field stop layer.
2 . The field stop structure of claim 1 , wherein the first conductivity type is N-type, and wherein each of the first field stop layer and the second field stop layers contains a dopant selected from a group consisting of phosphorus, arsenic, selenium, sulfur and combinations thereof.
3 . The field stop structure of claim 1 , wherein each of the plurality of trenches has a depth of 1 μm to 50 μm, and wherein the first field stop layer has a thickness of greater than 5 μm.
4 . The field stop structure of claim 1 , wherein a ratio of a width of each trench to a spacing between adjacent trenches is 1/50 to ½.
5 . The field stop structure of claim 1 , wherein the field stop structure has a carrier concentration greater than that of the silicon substrate.
6 . A reverse conducting insulated gate bipolar transistor (IGBT) semiconductor device comprising the field stop structure of claim 1 , the semiconductor device being integrated with an IGBT device and a fast recovered diode (FRD), the semiconductor device further comprising:
a first electrode region of the FRD consisting of a polysilicon or an epitaxial layer of the first conductivity type formed in the plurality of trenches;
a collector region of the IGBT device consisting of ion implantation regions of a second conductivity type formed in top portions of the second field stop layers; and
a back-side metal layer formed on the back side of the silicon substrate, the back-side metal layer being connected with the collector region of the IGBT device and the first electrode region of the FRD and serving as an electrode for the collector region of the IGBT device and the first electrode region of the FRD.
7 . A method for forming field stop structure, comprising:
forming a plurality of trenches ion a back side of a silicon substrate having a first conductivity type;
performing, by using ions of the first conductivity type, a vertical implantation and multiple steps of tilted implantations on the back side of the silicon substrate; and
performing an annealing process to activate and cause diffusion of the ions so as to form a laterally continuous first field stop layer in a portion of the silicon substrate at bottom of the plurality of trenches and a plurality of second field stop layers, each second field stop layer being located between two adjacent trenches and being joined with the first field stop layer.
8 . The method of claim 7 , wherein the first conductivity type is N-type, and the second conductivity type is P-type.
9 . The method of claim 7 , wherein each of the plurality of trenches has a depth of 1 μm to 50 μm, and wherein the first field stop layer has a thickness of greater than 5 μm.
10 . The method of claim 7 , wherein a ratio of a width of each trench to a spacing between adjacent trenches is 1/50 to ½.
11 . The method of claim 7 , wherein the vertical implantation is performed with an energy of 200 KeV to 3000 KeV and a dose of 1e11 cm −2 to 1e14 cm −2 , and wherein the multiple steps of tilted implantations are performed with at least two different angles and an implantation dose of 2e11 cm −2 to 5e12 cm −2 .
12 . The method of claim 8 , wherein the N-type ions used in the vertical implantation are phosphorus ions and the N-type ions used in the tilted implantations are phosphorus ions or arsenic ions, and wherein the annealing process is a thermal annealing process performed at a temperature of 700° C. to 1250° C.
13 . The method of claim 8 , wherein the N-type ions used in the vertical implantation are selenium ions or sulfur ions and the N-type ions used in the tilted implantations are selenium ions or sulfur ions, and wherein the annealing process is a thermal annealing process performed for 1 hour to 10 hours at a temperature of 700° C. to 900° C.
14 . The method of claim 7 , wherein the annealing process is a laser annealing process.
15 . A method for manufacturing reverse conducting insulated gate bipolar transistor (IGBT) semiconductor device, the semiconductor device being integrated with an IGBT device and a fast recovered diode (FRD), the method comprising the steps of:
depositing a first dielectric film over a front side of a silicon substrate having a first conductivity type so as to protect the front side of the silicon substrate;
forming a plurality of trenches on a back side of the silicon substrate;
performing, by using ions of the first conductivity type, a vertical implantation and multiple steps of tilted implantations on the back side of the silicon substrate;
performing an annealing process to activate and cause diffusion of the ions so as to form a laterally continuous first field stop layer in a portion of the silicon substrate at bottom of the plurality of trenches and a plurality of second field stop layers, each second field stop layer being located between two adjacent trenches and being joined with the first field stop layer; and
forming a first electrode region of the FRD and a collector region of the IGBT device.
16 . The method of claim 15 , wherein the step of forming a first electrode region of the FRD and a collector region of the IGBT device comprises:
depositing a second dielectric film over the back side of the silicon substrate and etching back the second dielectric film such that the etched second dielectric film partially fills each of the plurality of trenches;
forming ion implantation regions of a second conductivity type, which serve as the collector region of the IGBT device, in top portions of the second field stop layers, by performing an implantation of ions of the second conductivity type into the back side of the silicon substrate;
removing the second dielectric film; and
filling a polysilicon or an epitaxial layer of the first conductivity type, which serves as the first electrode region of the FRD, in the plurality of trenches.
17 . The method of claim 16 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
18 . The method of claim 17 , wherein ions of the second conductivity type are boron ions and are implanted with an energy of 30 KeV to 100 KeV and a dose of 3e14 cm −2 to 5e15 cm −2 .
19 . The method of claim 17 , wherein the polysilicon or the epitaxial layer has a dopant concentration of 1e19 cm −3 to 5e20 cm −3 .
20 . The method of claim 15 , wherein the step of forming a first electrode region of the FRD and a collector region of the IGBT device comprises:
filling a polysilicon or an epitaxial layer of the first conductivity type, which serves as the first electrode region of the FRD, in the plurality of trenches; and
forming ion implantation regions of a second conductivity type, which serve as the collector region of the IGBT device, in top portions of the second field stop layers, by performing an implantation of ions of the second conductivity type into the back side of the silicon substrate.
21 . The method of claim 20 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
22 . The method of claim 21 , wherein the polysilicon or the epitaxial layer has a dopant concentration of 1e19 cm −3 to 5e20 cm −3 .
23 . The method of claim 21 , wherein ions of the second conductivity type are boron ions and are implanted with an energy of 30 KeV to 100 KeV and a dose of 3e14 cm −2 to 5e15 cm −2 .