Electronic device including a conductive electrode and a process of forming the same
An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.
1. A process of forming an electronic device comprising:
providing a semiconductor layer;
forming a first insulating layer over the semiconductor layer;
forming a first conductive electrode member over the first insulating layer;
forming a patterned second insulating layer over the first conductive electrode member, wherein the patterned second insulating layer defines an opening having a bottom; and
forming a conductive layer within the opening of the patterned second insulating layer, wherein the conductive layer fills only part, and not all, of the opening;
forming a gate electrode of a transistor over the semiconductor layer, wherein:
forming the gate electrode is performed after forming the first conductive electrode member; and
forming the second conductive electrode member is performed after forming the gate electrode; and
anisotropically etching the conductive layer to remove the conductive layer from the bottom of the opening, wherein:
anisotropically etching the conductive layer forms a second conductive electrode member;
the second conductive electrode member lies along only a part, and not all, of the bottom of the opening; and
the first conductive electrode member abuts the second conductive electrode member.
2. The process of claim 1 , further comprising:
providing a buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface, wherein the buried conductive region is disposed closer to the opposing surface than to the primary surface; and
forming a vertical conductive region adjacent to the primary surface of the semiconductor layer and extending toward the buried conductive region, wherein the vertical conductive region is electrically connected to the buried conductive region.
3. The process of claim 2 , further comprising forming a horizontally-oriented doped region adjacent to the primary surface of the semiconductor layer and the first insulating layer, wherein in a finished device, the vertical conductive region is electrically connected to the horizontally-oriented doped region.
4. The process of claim 2 , further comprising forming a third insulating layer along an exposed side of the second conductive electrode member, wherein:
forming the vertical conductive region is performed after forming the third insulating layer and comprises:
etching the semiconductor layer to define a trench adjacent to the primary surface and extending toward the buried conductive region, wherein the trench has a bottom; and
forming a conductive layer within the trench such that the conductive layer contacts the bottom of the trench, wherein the third insulating layer is disposed between the second conductive electrode member and the conductive layer.
5. A process of forming an electronic device comprising:
providing a semiconductor layer;
forming a first insulating layer over the semiconductor layer;
forming a first conductive electrode member over the first insulating layer;
forming a gate electrode;
forming a source region;
forming a second conductive electrode member overlying and spaced apart from the semiconductor layer, wherein:
the first conductive electrode member abuts the second conductive electrode member;
the second conductive electrode member has a first end and a second end opposite the first end; and
each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member;
forming a second insulating layer overlying the first conductive electrode member, the gate electrode, and the second conductive electrode member;
forming first contact openings for the gate electrode and the second conductive electrode member;
patterning the second insulating layer to define a second contact opening to the source region, wherein patterning the second insulating layer is performed at a different time than forming the first contact openings;
forming conductive plugs within the first and second contact openings, wherein in a finished device, the source region is electrically connected to the second conductive electrode member.
6. The process of claim 5 , wherein the second insulating layer defines an opening having a bottom, and wherein the second conductive electrode member is formed within the opening of the second insulating layer.
7. The process of claim 5 , wherein:
forming the gate electrode is performed after forming the first conductive electrode member; and
forming the second conductive electrode member is performed after forming the gate electrode.
8. The process of claim 5 , wherein:
the first conductive electrode member has an uppermost point that lies at a first elevation;
the second conductive electrode member has an uppermost point that lies at a second elevation; and
the gate electrode has an uppermost point that lies at a third elevation that is closer to the second elevation than to the first elevation.
9. The process of claim 5 ,
wherein forming the conductive plugs comprises:
forming a first conductive plug that abuts the gate electrode within one of the first contact openings; and
forming a second conductive plug that abuts the second conductive electrode member,
wherein the first contact openings are formed at a same time.
10. The process of claim 9 , wherein a centerline of the trench intersects the vertical conductive region and the second conductive plug.
11. The process of claim 5 , further comprising:
providing a buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface, wherein the buried conductive region is disposed closer to the opposing surface than to the primary surface; and
forming a vertical conductive region adjacent to the primary surface of the semiconductor layer and extending toward the buried conductive region, wherein the vertical conductive region is electrically connected to the buried conductive region.
12. The process of claim 11 , further comprising forming a third insulating layer along an exposed side of the second conductive electrode member, wherein:
forming the vertical conductive region is performed after forming the third insulating layer and comprises:
etching the semiconductor layer to define a trench adjacent to the primary surface and extending toward the buried conductive region, wherein the trench has a bottom; and
forming a conductive layer within the trench such that the conductive layer contacts the bottom of the trench, wherein the third insulating layer is disposed between the second conductive electrode member and the conductive layer.
13. The process of claim 12 , further comprising etching the conductive layer to form a vertical conductive region within the trench, wherein an uppermost point of the vertical conductive region lies at an elevation below the second end of the second conductive electrode member.
14. The process of claim 13 , wherein at least a portion of an uppermost surface of the vertical conductive region lies at an elevation below an elevation of a bottom of the first conductive electrode member.
15. The process of claim 13 , wherein the vertical conductive region extends to an elevation no higher than the primary surface.
16. The process of claim 13 , further comprising forming a fourth insulating layer within a remaining portion of the trench.
17. A process of forming an electronic device comprising:
providing a semiconductor layer;
forming a first insulating layer over the semiconductor layer;
forming a first conductive electrode member over the first insulating layer;
forming a gate electrode over the semiconductor layer;
forming a patterned second insulating layer over the first conductive electrode member, wherein the patterned second insulating layer defines an opening having a bottom, and wherein the opening exposes the first conductive electrode member; and
forming a second conductive electrode member within the opening of the patterned second insulating layer, wherein:
the second conductive electrode member lies along only a part, and not all, of the bottom of the opening; and
the first conductive electrode member abuts the second conductive electrode member.
18. The process of claim 17 , wherein forming the gate electrode is performed after forming the first conductive electrode member and before forming the second conductive electrode member.
19. The process of claim 17 , wherein the bottom of the opening lies below a top surface of the first conductive electrode member.
20. The process of claim 17 , wherein forming the gate electrode is performed after forming the first conductive electrode member, and wherein forming the second conductive electrode member is performed after forming the gate electrode.