Blind via edge castellation

1. An apparatus comprising:

a substrate comprising a plurality of insulating layers and a plurality of conductive layers separated by said insulating layers, wherein (i) a first pattern in a first of said conductive layers extends to an edge castellation in said substrate, (ii) a second pattern in a second of said conductive layers extends to said edge castellation and (iii) said first conductive layer is on a solder side of said substrate;

a plating disposed in said edge castellation that connects said first pattern to said second pattern, wherein said plating in said edge castellation extends at most between a subset of said conductive layers;

a circuit mounted on said substrate from said solder side and electrically connected to said edge castellation; and

a solder layer disposed on said first conductive layer and configured to (i) flow into said edge castellation and (ii) attach said substrate to a surface of a motherboard, wherein said first conductive layer is parallel to said surface of said motherboard when said substrate is attached to said motherboard.

2. The apparatus according to claim 1 , further comprising an additional plating in an additional edge castellation that extends between two outermost layers of said conductive layers.

3. The apparatus according to claim 2 , wherein said additional plating in said additional edge castellation carries a low frequency signal.

4. The apparatus according to claim 3 , wherein a frequency of said low frequency signal is below 500 megahertz.

5. The apparatus according to claim 1 , further comprising one or more additional edge castellations and respective platings that extend at most between said subset of said conductive layers.

6. The apparatus according to claim 1 , wherein one or more of said conductive layers comprise a non-conductive area aligned to a half-cylinder defined by said edge castellation.

7. The apparatus according to claim 1 , wherein said second pattern comprises (i) a pad connected to said plating and (ii) a non-conductive area that isolates said pad from a rest of said second pattern.

8. The apparatus according to claim 1 , wherein said second pattern comprises (i) a pad connect to said plating and (ii) a trace connected to said pad.

9. The apparatus according to claim 1 , wherein said first conductive layer is an outermost one of said conductive layers on said solder side of said substrate.

10. The apparatus according to claim 1 , wherein said first pattern and said second pattern are separated by at most one of said insulating layers.

11. The apparatus according to claim 1 , wherein said plating in said edge castellation carries a high frequency signal.

12. The apparatus according to claim 11 , wherein a frequency of said high frequency signal is above one gigahertz.

13. The apparatus according to claim 12 , wherein a length of said edge castellation is configured to reduce stub-like characteristics of said plating on said high frequency signal.

14. The apparatus according to claim 1 , wherein said substrate comprises one of (i) a printed circuit board and (ii) a multilayer ceramic board.

15. The apparatus according to claim 1 , wherein a joint formed by said solder layer in said edge castellation is visually inspectible after said substrate is attached to said motherboard.

16. The apparatus according to claim 1 , further comprising a heat sink mounted on another side of said substrate opposite said solder side of said substrate.

17. The apparatus according to claim 1 , wherein said first pattern in said first conductive layer comprises a land gird array.

18. The apparatus according to claim 1 , wherein all castellations in said substrate extend through said first conductive layer.

19. The apparatus according to claim 1 , wherein at least two of said conductive layers have different thicknesses.

20. A method of communicating a signal, comprising the steps of:

generating said signal in a circuit, wherein (i) said circuit is mounted on a substrate from a solder side of said substrate and is electrically connected to an edge castellation, (ii) said substrate comprises a plurality of insulating layers and a plurality of conductive layers separated by said insulating layers, a first pattern in a first of said conductive layers extends to said edge castellation in said substrate, a second pattern in a second of said conductive layers extends to said edge castellation, and said first conductive layer is on said solder side of said substrate, (iii) a plating is disposed in said edge castellation that connects said first pattern to said second pattern and said plating in said edge castellation extends at most between a subset of said conductive layers, (iv) a solder layer is disposed on said first conductive layer and is configured to flow into said edge castellation and attach said substrate to a surface of a motherboard, and (v) said first conductive layer is parallel to said surface of said motherboard when said substrate is attached to said motherboard; and

transferring said signal through said first pattern in said first conductive layer, said plating in said edge castellation and said solder layer to said motherboard.

21. A method for fabricating an apparatus, comprising:

fabricating a substrate comprising a plurality of insulating layers and a plurality of conductive layers separated by said insulating layers, wherein (i) a first pattern in a first of said conductive layers extends to an edge castellation in said substrate, (ii) a second pattern in a second of said conductive layers extends to said edge castellation and (iii) said first conductive layer is on a solder side of said substrate;

fabricating a plating disposed in said edge castellation that connects said first pattern to said second pattern, wherein said plating in said edge castellation extends at most between a subset of said conductive layers;

mounting a circuit on said substrate from said solder side and electrically connected to said edge castellation; and

fabricating a solder layer disposed on said first conductive layer and configured to (i) flow into said edge castellation and (ii) attach said substrate to a surface of a motherboard, wherein said first conductive layer is parallel to said surface of said motherboard when said substrate is attached to said motherboard.

22. The method according to claim 21 , further comprising:

fabricating an additional plating in an additional edge castellation that extends between two outermost layers of said conductive layers.

23. The method according to claim 21 , further comprising:

fabricating one or more additional edge castellations and respective platings that extend at most between said subset of said conductive layers.

24. The method according to claim 21 , wherein one or more of said conductive layers comprise a non-conductive area aligned to a half-cylinder defined by said edge castellation.

25. The method according to claim 21 , wherein said second pattern comprises (i) a pad connected to said plating and (ii) a non-conductive area that isolates said pad from a rest of said second pattern.

26. The method according to claim 21 , wherein said second pattern comprises (i) a pad connect to said plating and (ii) a trace connected to said pad.

27. The method according to claim 21 , wherein said first conductive layer is an outermost one of said conductive layers on said solder side of said substrate.

28. The method according to claim 21 , wherein said first pattern and said second pattern are separated by at most one of said insulating layers.

29. The method according to claim 21 , wherein said plating in said edge castellation carries a high frequency signal.